Question

Experiment #4 Design and create a simulation waveform for a 5 out of 16 event detector using Verilog. This system will assert output to 1 when exactly 5 out of the last 16 serial events (value of input at the rising edges of clock) have been 1s. Here is an example timing diagram: CLK IN 1 2 3 4 6 OUT

Answer 1

Solution:

The design is implemented and simulated in Verilog

//---------- Code Starts here -----------//

module detect(clk,rst,IN,OUT);
input clk,rst,IN;
output reg OUT;
reg [4:0] count16,count5;
  
always @(posedge clk or posedge rst)begin
if(rst==1'b1) begin
count16<=0;
count5<=0;
OUT<=0;
end
else begin
count16<=count16+1'b1;
if(IN==1'b1) count5<=count5+1;
else count5<=count5;
  
if(count5==5) OUT<=1;
  
end
end
  
endmodule

//-------------------- END -----------------//

Test bench:

//----------------- Test Bench ------------------//

module tb();
reg clk,rst,IN;
wire OUT;
  
detect uut(.*);
initial begin
clk=0;rst=0;IN=0;#10;
rst=1;#2
rst=0;IN=1;#3;
IN=1;#3;
IN=1;#3;
IN=0;#3;
IN=1;#3;
IN=0;#3;
IN=1;#3;
IN=1;#3;
IN=1;#3;
IN=0;#3;
IN=0;#3;
IN=1;#200 $finish;
end
always #1 clk=~clk;
endmodule

//--------------------- END ----------------------//