Fro problem in this section, unless otherwise indicated, all allowable datapath components...

Fro problem in this section, unless otherwise indicated, all allowable datapath components are from Figure 5.21 and Figure 5.27, and controller design can end after deriving the FSM. Use the RTL design process for problem that state the need to “design” a system.

Using a timer, design a display system that reads the ASCII characters from a 64-word 8-bit register file RF and writes each word to a 2-row LED-based display having 32 characters per row, doing so 100 limes per second. The display has an 8-bit input A for the ASCII character to be displayed, a single-bit input row where 0 or 1 denotes the top or bottom row respectively, a 5-bit input col that indicates a column in the row, and an enable input en whose change from 0 to 1 causes the character to be displayed in the given row and column. The system should write RF[0| through RF[15] to row 0’s columns 0 to 15 respectively, and RF[16] to RF [31] to row 1

Figure 5.21 A basic datapath component library.

Figure 5.27 More datapath components for the library of Figure 5.21.