Question

Using the sequences of 32-bit memory read references, given as word addresses in the following table:

6

214

175

214

6

84

65

174

64

105

85

215

For each of these read accesses, identify the binary address, the tag, the index, and whether it experiences a hit or a miss, for each of the following cache configurations. Assume the cache is initially empty.

1. A direct-mapped cache with 16 one-word blocks.
2. A direct-mapped cache with two-word blocks and a total size of eight blocks.
3. A fully associative cache with two-word blocks and a total size of eight words. Use LRU replacement.
4. A 2-way set associative cache with one-word block size and total size of 8 words, while applying LRU replacement policy.

Answer 1

Solution

B)

As per the question we assume cache is initially empty

total cache size = 8 blocks that means it using 2 word block

1 bit assigned for word offset,

3 bits assigned for block selection that means 3 bits for index, remaining is for Tag

Address (word)	Address(Hex)	Cache Tag	Index	Cache Data	Hit/Miss
6	0x00000000000110	0x0000000000	011	M(6) M(7)	Miss
214	0x00000011010110	0x0000001101	011	M(6) M(7) replaced by M(214) M(215)	Miss
175	0x00000010101111	0x0000001010	111	M(174) M(175)	Miss
214	0x00000011010110	0x0000001101	011	M(214) M(215)	Hit
6	0x00000000000110	0x0000000000	011	M(214) M(215) replaced by M(6) M(7)	Miss
84	0x00000001010100	0x0000000101	010	M(84) M(85)	Miss
65	0x00000001000001	0x0000000100	000	M(64) M(65)	Miss
174	0x00000010101110	0x0000001010	111	M(174) M(175)	Hit
105	0x00000001101001	0x0000000110	100	M(104) M(105)	Miss
85	0x00000001010101	0x0000000101	010	M(84) M(85)	Hit
215	0x00000011010111	0x0000001101	011	M(6) M(7) replaced by M(214) M(215)	Miss

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solved one question, really sorry for that

please post remaining question separately, love to answer

all the best