Question

If I have a problem set like so: Below is a list of 64-bit memory address...

If I have a problem set like so:

Below is a list of 64-bit memory address references, given as word addresses.
3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253

5.2.1

BLOCK SIZE: 1 word

CACHE SIZE: 16 1-word blocks


a) For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.

b) For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.

c) You are asked to optimize a cache design for the given references. There are three direct-mapped cache design possible, all with a total of eight words of data. Which cache provides best performance?

a. C1 has 1-word blocks

b. C2 has 2-word blocks

c. C3 has 4-word blocks

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Answer #1

Cache À Memory address = 64 bit. Block size = l word .: Word Offset - Blocker- o bit Offset Total # of block in, 16 Index off4) 2: 0010 Block #:2. Tag = 0 This is a miss . (V) 1913 1011!!! y Block #=15 Тая: охв. This is a nuss. wi) 88 = 1011000 Blockx) 44 101100 I L Block # -12. Tag = 0x2. This is a miss. xi) 186 10111010 5 Block #=10 Tag=0xB. This is a miss. xii) 253 = 11(ii) 180 = 10110100 Block #:22. Tag: OxB. This is a miss. Gji) 43 = 101011 Block # = 5, Tag=0x2. This is aniss. (iv) a = 0010ON Let us first calculate the cache performance when block size = 4 word. Index - 2 bits, Block offset=2bit, Tag-60 bits. ;)

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