Question

1. Implement this ALU in VHDL: a (7:0) b (7:0) Logic Unit Mux y (7:0) Arithmetic Unit sel (3) cin sel (3:0) Function Transfera Increment a Decrement a Transfer b Increment b Decrement b Add a and b Add a and b with carr Complement a Complement b AND OR NAND NOR XOR Se eration Unit 0001 0010 0011 0100 0101 01 10 | y <= a+b 0111 1000 | y<= 1001| y<= NOT b 1010 | y<= a AND b 1011 1100 | y <= a NAND b 110| | y <= a NOR b 1110 | y<= a XOR b y<= a-1 Arithmetic y<= b+1 y<= b-1 <= a+b-cin NOT a y<= a OR b Logic NOR

Answer 1

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Tb_alu IS
END Tb_alu;
ARCHITECTURE behavior OF Tb_alu IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu
PORT(
inp_a : IN signed(3 downto 0);
inp_b : IN signed(3 downto 0);
sel : IN std_logic_vector(2 downto 0);
out_alu : OUT signed(3 downto 0));
END COMPONENT;
--Inputs
signal inp_a : signed(3 downto 0) := (others => '0');
signal inp_b : signed(3 downto 0) := (others => '0');
signal sel : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal out_alu : signed(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)

uut: alu PORT MAP (
inp_a => inp_a,
inp_b => inp_b,
sel => sel,
out_alu => out_alu
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
inp_a <= "1001";
inp_b <= "1111";
sel <= "000";
wait for 100 ns;
sel <= "001";
wait for 100 ns;
sel <= "010";
wait for 100 ns;
sel <= "011";
wait for 100 ns;
sel <= "100";
wait for 100 ns;
sel <= "101";
wait for 100 ns;a
sel <= "110";
wait for 100 ns;
sel <= "111";
end process;
END