Question

this is hardware soft co-design class

thank you

04. Design a 4:1 Mux using case statement (behavioral modeling). Design 16:1 Mux concept of hierarchy by utilizing the designed 4:1 Mux. Write the stimulus for 10:1 mu Point).

Answer 1

4:1 MUX using case statement -

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity multiplexer_case_basic is
    port(
        din : in STD_LOGIC_VECTOR(3 downto 0);
        sel : in STD_LOGIC_VECTOR(1 downto 0);
        dout : out STD_LOGIC
         );
end multiplexer_case_basic;


architecture multiplexer_case_arc of multiplexer_case_basic is
begin

    mux : process (din,sel) is
    begin
        case sel is
            when "00" => dout <= din(3);
            when "01" => dout <= din(2);
            when "10" => dout <= din(1);
            when others => dout <= din(0);
        end case;
    end process mux;

end multiplexer_case_arc;

design of 16:1 MUX using 4:1 MUX

code -

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity basic_4x1mux is
port(a,b,c,d : in std_logic;
S0,s1 : in std_logic;
q : out std_logic);
end basic_4x1mux;

Architecture basic_4x1mux1 of basic_4x1mux is
Begin
Process(a,b,c,d,s0,s1)
Begin

If s0 ='0' and s1 ='0' then q <= a;
Elsif s0 ='1' and s1 ='0' then q <= b;
elsif s0 ='0' and s1='1' then q <= c;
else q <=d;
end if;
End process;
End basic_4x1mux1;

Main program -

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity basic_16x1mux is
port(a:in std_logic_vector(15 downto 0);

s: in std_logic_vector(3 downto 0);

Z:out std_logic);

End basic_16x1mux;

Architecture basic_16x1mux1 of basic_16x1mux is
signal z1,z2,z3,z4:std_logic;

component basic_4x1mux is

port(a,b,c,d,s0,s1:in std_logic;

Q:out std_logic);

End component;

Begin

M1: basic_4x1mux port map(a(0),a(1),a(2),a(3),s(0),s(1),z1);
m2: basic_4x1mux port map(a(4),a(5),a(6),a(7),s(0),s(1),z2);
m3: basic_4x1mux port map(a(8),a(9),a(10),a(11),s(0),s(1),z3);
m4: basic_4x1mux port map(a(12),a(13),a(14),a(15),s(0),s(1),z4);
m5: basic_4x1mux port map(z1,z2,z3,z4,s(2),s(3),z);

End basic_16x1mux1;