HomeworkLib
Question

0. (10 Points) A four-core i7 has a 8 MB L3 cache 8-way set associative of block size 32 bytes. It uses 30-bit block address (36-bit physical address, 6-bit block offset). What is the addressing organization of L3? ANSWER Block Address - Block offset Index Tag-
engineering   Computer-Science   
0 0
Add a comment Improve this question Transcribed image text
Next > < Previous
Sort answers by oldest

Homework Answers

Answer #1

B) Bte blocr cize 2. 2 : 교bccKS 2 6 bit 14 Get indux4bits TA GCC t)1 bits

0 0
Add a comment
Know the answer?
Add Answer to:
0. (10 Points) A four-core i7 has a 8 MB L3 cache 8-way set associative of...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Log In

Sign Up

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions

  • Q2. Consider a four-way set associative cache with a data size of 64 KB. The CPU...

    Q2. Consider a four-way set associative cache with a data size of 64 KB. The CPU generates a 32-bit byte addressable memory address. Each memory word contains 4 bytes. The block size is 16 bytes. Show the logical partitioning of the memory address into byte offset, cache index, and tag components.

  • A 256kiB (2^18 bytes) cache has a block size of 32 bytes and is 32-way set-associative....

    A 256kiB (2^18 bytes) cache has a block size of 32 bytes and is 32-way set-associative. How many bits of a 32-bit address will be in the Tag, Index, and Bock Offset?

  • question 2 and 3 2. Determine how many sets of cache blocks will be there for...

    question 2 and 3 2. Determine how many sets of cache blocks will be there for the following Cache memory size (in bytes) Direct Mapped Blocks Size (in bits) 32 64 218 2-way Set Associative Block Size (in bits) 32 64 A 2A6 [0.5 * 16 = 8] 4-way Set Associative Block Size (in bits) 32 64 SK 64K 256K 3. The physical memory address generated by a CPU is converted into cache memory addressing scheme using the following mapping...

  • Given a 32-bit address, calculate the following values for a two-way set associative for: Cache size:...

    Given a 32-bit address, calculate the following values for a two-way set associative for: Cache size: 32KB Block size: 64B i) The number of bits in the block offset field. ii) The number of index bits. iii) The number of sets in the cache. iv) The number of tag bits.

  • 2. Set Associative Cache (36 pts) Given the following address access stream, please answer 2.1, 2.2...

    2. Set Associative Cache (36 pts) Given the following address access stream, please answer 2.1, 2.2 and 2.3. All the addresses are 32-bit. The sequence is shown below. Load Load Store Store Load 0x22160788 Ox09000E40 0x1265024C 0x22160484 0x1265014C 2.1 (11 pts) A 512 bytes, 2-way writeback cache. The cache line size is 64 bytes. Please calculate the number of bits used for tag, set index, and offset. Number of tag bits = Number of index bits = Number of offset...

  • Cache Layout: A processor has a separate D-cache and an I-cache. D-cache: 64KB, 4-way set associative,...

    Cache Layout: A processor has a separate D-cache and an I-cache. D-cache: 64KB, 4-way set associative, block size of 1 word, write-back policy I-cache: 32KB, direct mapped cache, block size of 1 word The processor uses the LRU algorithm for its replacement policy. Answer the following questions. Make sure that you account for all the book -keeping bits. A word is 4 bytes (a) Calculate the number of tag, index and offset bits for the D-cache. (b) Calculate the number...

  • please solve e & f for this question. 1. (40 points) The Corei7-6700K microprocessor has 3...

    please solve e & f for this question. 1. (40 points) The Corei7-6700K microprocessor has 3 cache levels about the L2 cache per core and the main memory: (more detailed information can be found at: http://www.cpu-world.com/CPUs/Core i7/Intel-Core%2017-6700.html The following is the information Memory is byte addressable Maximum memory capacity is 64 GB (G=230). Cache capacity is 256 KB (K=210) 4-way set associative is used - Block offset size is 6 bits. If CPU has generated the physical address (411234)10, what...

  • Make an assumption that your cache is either: Fully associative Direct mapped Two-way set-associative Four-way set-associative...

    Make an assumption that your cache is either: Fully associative Direct mapped Two-way set-associative Four-way set-associative determine: the size of the Tag and Word for Associative cache; OR the size of the Tag, Line, and Word for Direct-Mapped Cache ; Or the size of Tag, Set, and Word for K-Way Set-Associative Cache. You may make any assumptions necessary including the number of Words in each block (recommend 2 or 4 or 8)

  • Consider a 32-bit microprocessor that has on-chip 16Kbyte four-way set associative cache. Assume that cache has...

    Consider a 32-bit microprocessor that has on-chip 16Kbyte four-way set associative cache. Assume that cache has a line size of four 32-bit words. How many number of set are there? Sketch block diagram of this cache showing its organization. Where in the cache is the word from memory location ABCDE7F4.

  • ) Consider an 8-way associative 64 Kilo Byte cache with 32 byte cache lines. Assume memory...

    ) Consider an 8-way associative 64 Kilo Byte cache with 32 byte cache lines. Assume memory addresses are 32 bits long. a). Show how a 32-bit address is used to access the cache (show how many bits for Tag, Index and Byte offset). b). Calculate the total number of bits needed for this cache including tag bits, valid bits and data c). Translate the following addresses (in hex) to cache set number, byte number and tag (i) B2FE3053hex (ii) FFFFA04Ehex...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT