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400 MHz CPU with 5 stage execution, |
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A) 1+1+0+8+0= 10 clock cycle
B)400MHz = 400 Million cycles per second=400,000,000
total no. of clock cycle per instructions=4
For every 10 cycles one instruction is completed
So, in one second the total 400,000,000/10 = 40,000,000 instruction are completed if not pipelined
C) If it is pipelined then the first instruction is completed in the first 10 clock cycle, and for every next clock cycle one instruction gets completed.
So, 400,000,000-10= 399,999,990 instructions are completed.
D) If it is pipelined and execution stage superscalar then two stage per clock cycle is executed i.e. 5 cycles for one instruction and pipeline the consecutive instructions it results in
400,000,000-5= 399,999,995 instructions will be completed in a second.
400 MHz CPU with 5 stage execution, 1 clock Instruction fetch 1 clock Decode 0 clock...
A 5-Stage pipeline is composed
of the following stages Instruction Fetch (IF), Decode (DE),
Execute (EX), Memory Access (ME) and Register Write-back (WB).
Assume the pipeline does not have a branch prediction unit, does
not have superscalar support and does not support out of order
execution. Assume that all memory accesses are in the L1 cache and
therefore do not introduce any stalls. Show a pipeline diagram that
shows the execution of each stage for the assembly code below. Also...
We found that the instruction fetch and memory stages are the
critical path of our 5-stage pipelined MIPS CPU. Therefore, we
changed the IF and MEM stages to take two cycles
while increasing the clock rate. You can assume that the register
file is written at the falling edge of the clock.
Assume that no pipelining optimizations have been made, and that
branch comparisons are made by the ALU. Here’s how our pipeline
looks when executing two add instructions:
Clock...
A particular (fictional) CPU has the following internal units and timings: 1. IFD: Instruction fetch + decode : 160 ps 2. RR: Register read 80 ps 3. ALU: 240 ps 4. MA : memory access: 160 ps (assuming cache) 5. RW : register write : 80 ps There are 5 basic instruction types: 1. LOAD : IFD+RR+ALU+MA+RW 720 ps 2. STORE: IFD+RR+ALU+MA : 640 ps 3. ARITHMETIC: IFD+RR+ALU+RW : 560 4. BRANCH: IFD+RR+ALU : 480 ps 5. MEMOP: IFD+RR+MA+ALU+MA :...
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QUESTION 2 The pipeline in the ARMI1 CPU is shown in Figure Q2(a). There are three possible (a) paths through the pipeline. The path of the execution depends on what type of instruction is executing (b) Instruction Fetoh Write Decode Execute Back Address DCI Dcz WBIS FE1 FE2 Decode Issue Shif ALU Saturate WBes MAC2 МАСI МАСУ Figure Q2(a) (i) Identify the number of stages for the ARMI1 CPU pipelines....
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you..
QUESTION 2 The pipeline in the ARMI1 CPU is shown in Figure Q2(a). There are three possible (a) paths through the pipeline. The path of the execution depends on what type of instruction is executing (b) Instruction Fetoh Write Decode Execute Back Address DCI Dcz WBIS FE1 FE2 Decode Issue Shif ALU Saturate WBes MAC2 МАСI МАСУ Figure Q2(a) (i) Identify the number of stages for the ARMI1 CPU pipelines. [1...
Consider a standard 5-stage MIPS pipeline of the type discussed
during the class sessions: IF-
ID-EX-M-WB.
Assume that forwarding is not implemented and only the hazard
detection and stall logic is
implemented so that all data dependencies are handled by having the
pipeline stall until the
register fetch will result in the correct data being fetched.
Furthermore, assume that the memory is written/updated in the first
half of the clock cycle
(i.e. on the rising edge of the clock) and...
b. A microprocessor has an instruction set that consists of 117 instructions, which need fetch, decode, read operand, execute, write and interrupt stages. Assume that as an average, each stage requires three micro- operations to complete. Also, assume that the control memory is N bits wide (i.e., control field bits + address selection field bits + address-one bits + address-two bits N bits). The control field bits are 15 and there are 15 flags to be monitored. i. How many...
computer architecture and organization
Figure Q20 shows a space time diagram to execute n instructions by CAOTM processor The instruction cycle comprises 4 steps; fetch (F), decode (D), execute (E), and write back (W). Assume 1 clock cycle= 10 ns. 10 20 30 40 50 60 70 80 90 100 110 120 130 Time, ns Cycle Instruction- 1 2 3 4 6 7 8 9 10 11 13 1 F D E E W 2 F E E W D...
Q4. CISC/RISC and Cache Memory (24pts) Q4-1. Assume that UltraSpark-like processor has an L1 cache with the following specifications: 40-bit wide address and 64-bit wide data busses On-chip instruction cache Cache is 16K bytes, organized as a 2-way set associative Cache line (block) size = 64 bytes 200 MHz clock frequency Average cache hit rate = 90% Instructions located in cache execute in 1 clock cycle Instructions that are not found in the on-chip cache will cause the processor to...
12 po Iw add Question 11 The dassic five-stage pipeline MIPS architecture is used to execute the code fragments in this problem. Assume the followings: • The architecture fully supports forwarding • Register write is done in the first half of the clock cycles register read is performed in the second half of the clock cyde. Branches are resolved in the third stage of the pipeline and the architecture does not utilize any branch prediction mechanism Register R4 is initially...