Question

4.19 Describe how the unstable condition S= R=1 is avoided in the storage latch of the following: (a) D latch (c) T flip-flop (b) JK flip-flop

Answer 1

ii) Do latch The D- latch or transparent a simple extension of the latch that removes the of invalid input states. latch is gated SR possibility S=D oth Doga R=0 Since the gated SR latch allows us to latch the output without using the sor R inputs, we can remove one input and automatically make it the inverse of the remaining input. The D latch out or puts the D input whenever the enable line is high, otherwise the output is whatever the D infut wal

when the Enable input was lost high.' Enable Latchled Latched (0) J-k Flip flops CLK O The sequential operation of JK flip flop is exactly some as SR flipflop. The difference is that J-k flip flops has no invalid or forbidden input states

Плол of the SR latch even when sand & are both at logic 1. As from above circuit TES and K=R. The twoa.input AND gates of gated SR bistable have now been replaced by two 3-input NAND gates with the third input of each gate connected to the outputs at a and ã. This cross coupling of SR flip flops allows the invalid condition of s= 1 and R=1 to be used to produce "toogle action". of the circuit is now 'SET' the I input is inhibited by 'o' status of a through the lower NAND gates of the circuit is 'RESET' the x inkut is inhibited by the low status of a through

the upper N AND gate. As Q and a are always different we can use them to control the input. when both 9 and are equal to logic 1, the - JK flipflop toggles as shown. Truth Table CLK I J K l Q 1 ã l State Memory no change 1 Reset Q * o Set Q = 1 Това е

Thus Jk flip flop enables only one of its two input terminals, either SET or RESET to be active at any one time there by eliminating the invalid condition in SR latch circuit. (ii) T- Flipflops To flep flop also known as "Toggle flip-flop". To avoid the occurrence of intermediate state in SR flip flops, we provide only one input to flip flops then flip flop acts as a Toggle switch. Toggling means Changing the next state output to complement of the present state output."

I Data Qprev Praw "Next Next Truth Table Previous Next 7 Qeren Beren 01 0 I Lol 1 0 1 1 1 tl o 1 1 L1 | 1 gh the output Q=0 the the upper NAND is in enable state and lower NAND is in disable condition. This allows the trigger to poss the sinputs

to make the flip flop in SET state ie Q = 1 of the output Q=1, then the upper NAND is in disable state and lower NAND gate is in enable condition. This allows the trigger to pass R input to make the flip flops in RESET state i.e. Q=O. : In simple term when I input is low, then next state of I flip flop is some as present state and when Tinput is high and during positive transition of clock signal , next state of 9 flip flop is inverse of present state.