HomeworkLib
Question

Consider 512Kx8bits dynamic RAM chips where the memory access time is 2/3 of the memory cycle...

Consider 512Kx8bits dynamic RAM chips where the memory access time is 2/3 of the memory cycle time. These chips have an Address Bus, a bi-directional Data Bus, a Read/Write control line and a Chip Select line.

(a) Draw the diagram of a memory organization that will contain 4 megabytes, will have a 32-bit bi-directional data bus and will yield one word (32-bits) every access time if words are read from consecutive memory locations (in bursts). Clearly show and explain the number of memory chips used, how your design is capable of reading one word every memory read access time, and which bits in the address are used to select a word from your memory organization.

(b) For this memory organization, can one write a block of consecutive words faster than one every memory cycle time?

(c) Suggest a timing such that words are read faster than one every access time (assume that data appears on the memory chips’ data bus instantaneously at the time it becomes available).

engineering   Computer-Science   
0 0
Add a comment Improve this question Transcribed image text
Next > < Previous
Sort answers by oldest

Homework Answers

Answer #1

Consider 512Kx8bits dynamic RAM chips where the memory access time is 2/3 of the memory cycle time. These chips have an Address Bus, a bi-directional Data Bus, a Read/Write control line and a Chip Select line.c. We cannot read faser than one word every Access time.

0 0
Add a comment
Know the answer?
Add Answer to:
Consider 512Kx8bits dynamic RAM chips where the memory access time is 2/3 of the memory cycle...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Log In

Sign Up

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions

  • Memory organization a) Suppose that a 32MB system memory is built from 32 1MB RAM chips. How many...

    Memory organization a) Suppose that a 32MB system memory is built from 32 1MB RAM chips. How many address lines are needed to select one of the memory chips? Suppose a system has a byte-addressable memory size of 4GB. How many bits are required for each address? Suppose that a system uses 16-bit memory words and its memory built from 32 1Mx 8 RAM chips. How large, in words, is the memory on this system? Suppose that a system uses...

  • 2. Suppose that a 16M X 16 main memory is built using 512K X 8 RAM...

    2. Suppose that a 16M X 16 main memory is built using 512K X 8 RAM chips and memory is word addressable. a) How many RAM chips are necessary? ______ b) How many RAM chips are needed for each memory word? _______ c) How many address bits are needed for each RAM chip? _______ d) How many address bits are needed for all memory? _______ A digital computer has a memory unit with 24 bits per word. The instruction set...

  • 3. Memory organization: Consider 8 Mb SRAM chips with two different internal organizations, 8-bits and 16-bits...

    3. Memory organization: Consider 8 Mb SRAM chips with two different internal organizations, 8-bits and 16-bits wide. Show how each of these chips would be inter- connected (rows x columns) to construct a 32 MB memory with the following word a. 16-bit words widths: b. 32-bit words

  • Question 3 The access time of a cache is 80 ns and the access time of...

    Question 3 The access time of a cache is 80 ns and the access time of main memory is 1200 ns. We have 85% of instructions are directed to read while 15% is for writes. Hit ratio is 92%. A write through procedure is used. A. Give the average access time considering only the read requests B. Give average access time for both read and write requests. C. Give the overall hit ratio given the write cycle as well. Question...

  • Consider a memory hierarchy using one of the three organization for main memory shown in a...

    Consider a memory hierarchy using one of the three organization for main memory shown in a figure below. Assume that the cache block size is 32 words, That the width of organization b is 4 words, and that the number of banks in organization c is 2. If the main memory latency for a new access is 10 cycles, sending address time is 1 cycle and the transfer time is 1 cycle, What are the miss penalties for each of...

  • b) Compute the miss penalty to transfer 8 words cache block from DRAM, where it takes...

    b) Compute the miss penalty to transfer 8 words cache block from DRAM, where it takes 2 memory bus cycles to send the address, 25 memory bus cycles for DRAM access time and 3 memory bus cycles to send one word of data for the following three organizations: (i) Oneword-wide memory organization, (ii) Wide memory organization (4-word wide) and (iii) Interleaved memory organization (4 banks). Show all your work to get full credit.

  • VHDL code FIRST ACTIVITY (100/100) RANDOM MEMORY ACCESS (RAM) EMULATOR: The following dircuit is a memory...

    VHDL code FIRST ACTIVITY (100/100) RANDOM MEMORY ACCESS (RAM) EMULATOR: The following dircuit is a memory with 8 addresses, each address holding a 4-bit data. The memory positions are implemented by 4-bit registers. The resetn (active low) and clock signals are shared by all the registers. Data is written onto (or read from) one of the registers. wE rd 0 2 Memory Write (wr-rd = 1): The 4-bit input Din is written into one register. The address [2..0 signal selects...

  • 2) (25 points) Consider a hypothetical mieroprocessor generating 16-bit addresses with 32-bit data accesses (i.e. each access retrieves 32 bits for each address). a. What is the maximum memory ad...

    2) (25 points) Consider a hypothetical mieroprocessor generating 16-bit addresses with 32-bit data accesses (i.e. each access retrieves 32 bits for each address). a. What is the maximum memory address space (i.e., mmber of addresses) that the processor can access directly? What is the maximum memory capacity (in bytes) for this microprocessor? b. c. What is the last memory address that the CPU can access? Write your answer in decimal. What is the maximum memory address space that the processor...

  • 4B, 20%) compare performance of a Processor with cache vs. without cache. Assume an Ideal processor with 1 cycle memory access, CPI1 Assume main memory access time of 8 cycles Assume 40% instruct...

    4B, 20%) compare performance of a Processor with cache vs. without cache. Assume an Ideal processor with 1 cycle memory access, CPI1 Assume main memory access time of 8 cycles Assume 40% instructions require memory data access Assume cache access time of I cycle Assume hit rate 0.90 for instructiens, 0.80 for data Assume miss penalty (time to read memory inte cache and from cache to Processor with cache processor) is 10 cycles >Compare execution times of 100-thousand instructions: 4B,...

  • 6. Memory Access Time [15 points] Consider a MIPS processor that includes a cache, a main...

    6. Memory Access Time [15 points] Consider a MIPS processor that includes a cache, a main memory, and a hard drive. Access times of cache memory, main memory, and hard drive are 5 ns, 200 ns, and 1000 ns, respectively. Assume that cache memory is divided into instruction cache and data cache. Assume that data cache has a 90% hit rate. Assume that main memory has a 98% hit rate and hard drive is perfect (it has a 100% hit...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT