Question

4. The logical value 1 (HI) under the I2C protocol is considered “recessive”, while the logic 0 (LO) value is “dominant”. What does this mean and how is it implemented electrically, i.e., the Physical layer of the protocol?

Answer 1

As per Bit encoding:

1. Voltage difference → “dominant” bit == logical 0
2. No voltage difference → “recessive” bit == logical 1

When 2 nodes are transmitting at same time, Bus state can be determined as below:

NODE 1

	Dominant	Recessive
Dominant	Dominant	Dominant
Recessive	Dominant	Recessive

NODE 2

So,

1. When a node transmits dominant, it always hears dominant
2. When a node transmits recessive and hears dominant, then there is a bus conflict

Consider a case of CAN when no nodes are communicating, the bus "floats" to a particular state at the physical layer. This is the recessive state. Whenever a node drives, a dominant bit will override this state (hence the word "dominant").This is used within the protocol to allow non-destructive arbitration to occur, where the node with the lowest id "wins".

Dominant applies to 0 because if two arbitration ID's are being transmitted at the same time say 11110 & 11111 , (here first 4 bits of both ID's are same but having difference in 5th bit) the ID with the 0 will end up being transmitted. Transmission of the message with the larger arbitration ID will be tried again after the other message is done.

Electrical implementation at Physical layer:

Inter–Integrated Circuit bus i.e I2C is a Protocol which allows the connection of multiple slaves to a single master and multiple masters controlling single, or multiple slaves. I2C only uses two wires to transmit data between devices via open-drain (or open-collector) output drivers:

SDA (Serial Data) – The line for the master and slave to send and receive data.

SCL (Serial Clock) – The line that carries the clock signal.

  

It makes use of NMOS Transistors and a resistor is externally connected to the IC. If the input is logic high, the NMOS transistor provides a low-impedance connection to ground. But if the input is logic low, the NMOS looks like an open circuit, which means that the output gets pulled up to VDD through the external resistor. This arrangement leads to:

1. Occurance of nontrivial power consumption when the output is logic low, because current flows through the resistor, through the channel of the NMOS transistor, to ground (in the push-pull configuration, this current is blocked by the high impedance of the off-state PMOS transistor).
2. The output signal behaves differently when it is logic high because it is connected to VDD through a much higher resistance (usually at least 1 kΩ). This feature makes it possible to directly connect two (or more) open-drain drivers: even if one is logic low and the other is logic high, the pull-up resistor ensures that current does not flow freely from VDD to ground.