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A microprocessor has a decrement memory direct instruction, which subtracts 1 from the value in a...

A microprocessor has a decrement memory direct instruction, which subtracts 1 from
the value in a memory location. The instruction has five stages: fetch opcode (two bus
clock cycles), fetch operand address (five cycles), fetch operand (five cycles), subtract
1 from operand (four cycles), and store operand (two cycles).
a. By what amount (in percent) will the duration of the instruction increase if we have
to insert one bus wait state in each memory read and memory write operation?
b. Repeat assuming that the decrement operation takes 8 cycles instead of 4 cycles.

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