Question

1. Translate the following tasks into a single ARM instruction:

a. Add 32 times of the content of registers r0 and the content of r1 only if N is clear. Store the result in register r2

b. Subtract the content of register r0 from 0x990 and put the results in register r3 only if C is set and Z is clear.

c. Clear the 2nd least significant byte of the content of register r1, i.e., store (00000000)2 in it, and put the results in register r4. The result of the instruction must affect the value of the Current Program Status Register (CPSR).

Answer 1

MOV R5,#32 ;initializing counter

loop: ADDPL R2,R0,R1 ;adding contents of RO and R1 and saving the result in R2 only if N is clear

SUB R5,R5,#01 ;decrementing counter

BNE loop ;if Z is not set,that is ,counter is not zero then the branch will take place

RSBHI R3,R0,0x990 ; if C is set and Z is clear,contents of R0 will be subtracted from 0x990

BIC R4,R1,0b0000000011111111   ;getting content of the 2nd least significant byte of the content of register r1 and storing it into R4 by bit clearing the least significant byte.

SUB R4,R4,R1 ;this instruction will make the  2nd least significant byte of the content of register r1 zero and assuming that the  least significant byte of the content of register r1 is not 00000000,N flag in the CPSR will be set. ;