simulate and AND gate implimented only with NAND gates in verilog. Include verilog code

Question

Question

engineering Electrical-Engineering

Answer 1

Answer #1

Answered the question below.

If you have any doubt ask in the comment section.

Verilog code:

module andGate(a,b,y);

input a,b;

output y;

wire c;

nand(c,a,b);

nand(y,c,c);

endmodule

Answer 2

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