1. In a pipelined Y86 CPU, a conditional jump instruction creates what kind of problem? a)...
1. In a pipelined Y86 CPU, a conditional jump instruction creates what kind of problem?
a) none of these b) data dependency c) nonuniform partitioning d) control dependency e) latency
Homework Answers
d) control dependency
conditional jump instruction creates control dependency
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1. In a pipelined Y86 CPU, a conditional jump instruction
creates what kind of problem?
a)...
01. Consider the stagevise single cycle CPU with the circuit as given on the attached sheet....
01. Consider the stagevise single cycle CPU with the circuit as given on the attached sheet. The following are the latencies of each component: Instruction memory 180 ps Add 4 unit Mux Registers Main Control ALU Control ALU AND Shift Left2 Sign Extend Branch Adder Data Memory 60 ps 15ps 120 ps 50 ps, 25 ps, 150 ps 5 ps 10 ps(Shiftleft2jump also) 15 ps 60 ps 150 ps C) Do a stagewise latency analysis of the circuit. Write down...
400 MHz CPU with 5 stage execution, 1 clock Instruction fetch 1 clock Decode 0 clock...
400 MHz CPU with 5 stage execution, 1 clock Instruction fetch 1 clock Decode 0 clock data fetch 8 clock execution 0 clock write back. A. How many clocks to complete 1 instruction? B. How many instructions are completed in a second if not pipelined? C. How many instructions are completed in a second if pipelined? D. How many instructions are completed in a second if pipelined and execution stage superscalar?
Question Completion Status: QUESTION 22 What is the advantage of pipelining? A. It decreases instruction throughput...
Question Completion Status: QUESTION 22 What is the advantage of pipelining? A. It decreases instruction throughput B. it decreases instruction latency C. It makes the CPU more expensive OD. It increases instruction latency E. It increases instruction throughput QUESTION 23 What is the only instruction for which the MemWrite control signal is true? A. Iw B.SW C.slt D.add E beq QUESTION 24
A non-pipelined processor has a clock rate of 1 GHz and an average instruction takes 9...
A non-pipelined processor has a clock rate of 1 GHz and an average instruction takes 9 cycles to execute. The manufacturer has decided to design a pipelined version of this processor. For this purpose, the instruction cycle has been divided into five stages with the following latencies: Stage 1 – 2.0 ns,Stage 2 – 1.5 ns, Stage 3 – 1.0 ns, Stage 4 – 2.6 ns, Stage 5 – 1.9 ns. Each stage will require an extra 0.4 ns for...
(a) The control unit (CU) in the central processing unit (CPU) controls the data flow and operations in the CPU. Explain...
(a) The control unit (CU) in the central processing unit (CPU) controls the data flow and operations in the CPU. Explain the difference between the two methods used for designing the control unit. [6 marks] (b) Explain the difference between the direct and indirect addressing moods. [4 marks] (c) Explain how an instruction is fetched in the fetch decode execute cycle. [5 marks] (d) What is the difference between a 16-bit microprocessor and 32-bit Pentium microprocessors?
Page 4 3. Pipeline is an instruction-level parallel processing techni microprocessor systems. The instruction throughput can be dramaticallu increased by this key technique. However, there are so...
Page 4 3. Pipeline is an instruction-level parallel processing techni microprocessor systems. The instruction throughput can be dramaticallu increased by this key technique. However, there are so called hazard problems. (a) Branch instruction will introduce problems to a pipelined instruction execution. Explain how this may happen in a DLX machine, and state ONE strategy that can be used to resolve the problem (6 marks) (b) Data hazards occur in instruction execution in a pipelined machine. () What is meant by...
Part 1: A pipelined computer completes instructions more quickly by having more than one instruction at...
Part 1: A pipelined computer completes instructions more quickly by having more than one instruction at a time "in the pipeline." Explain what problem branch instructions cause with instruction pipelining. Describe one approach to overcoming this problem. Part 2: RISC computers generally execute more instructions per second than CISC computers. Describe the penalty or trade-off paid when adopting the RISC architecture. Part 3: When a cache hit to a cache on the CPU chip occurs on a memory write the...
A particular (fictional) CPU has the following internal units and timings: 1. IFD: Instruction fetch + decode : 160 ps...
A particular (fictional) CPU has the following internal units and timings: 1. IFD: Instruction fetch + decode : 160 ps 2. RR: Register read 80 ps 3. ALU: 240 ps 4. MA : memory access: 160 ps (assuming cache) 5. RW : register write : 80 ps There are 5 basic instruction types: 1. LOAD : IFD+RR+ALU+MA+RW 720 ps 2. STORE: IFD+RR+ALU+MA : 640 ps 3. ARITHMETIC: IFD+RR+ALU+RW : 560 4. BRANCH: IFD+RR+ALU : 480 ps 5. MEMOP: IFD+RR+MA+ALU+MA :...
Computer Architecture 14. Fill in the blanks below with the most appropriate term or concept discussed...
Computer Architecture 14. Fill in the blanks below with the most appropriate term or concept discussed in this chapter: A. ---------------The time required for the first result in a series of computations to emerge from a pipeline. B. ---------------This is used to separate one stage of a pipeline from the next. C. ---------------Over time, this tells the mean number of operations completed by a pipeline per clock cycle. D. ---------------The clock cycles that are wasted by an instruction-pipelined processor due...
Consider a hypothetical computer with an instruction set of only two n-but instructions. The firs...
Consider a hypothetical computer with an instruction set of only two n-but instructions. The first bit specifies the opcode, and the remaining bits specify one of the 2-1 n-bit words of main memory. The two instructions are as follows: SUBS X: Subtract the contents of location X from the accumulator, and store the result in location X and the accumulator JUMP X: Place address X in Program Counter A word in memory may contain either an instruction or a binary...
01. Consider the stagevise single cycle CPU with the circuit as given on the attached sheet. The following are the latencies of each component: Instruction memory 180 ps Add 4 unit Mux Registers Main Control ALU Control ALU AND Shift Left2 Sign Extend Branch Adder Data Memory 60 ps 15ps 120 ps 50 ps, 25 ps, 150 ps 5 ps 10 ps(Shiftleft2jump also) 15 ps 60 ps 150 ps C) Do a stagewise latency analysis of the circuit. Write down...
Question Completion Status: QUESTION 22 What is the advantage of pipelining? A. It decreases instruction throughput B. it decreases instruction latency C. It makes the CPU more expensive OD. It increases instruction latency E. It increases instruction throughput QUESTION 23 What is the only instruction for which the MemWrite control signal is true? A. Iw B.SW C.slt D.add E beq QUESTION 24
Page 4 3. Pipeline is an instruction-level parallel processing techni microprocessor systems. The instruction throughput can be dramaticallu increased by this key technique. However, there are so called hazard problems. (a) Branch instruction will introduce problems to a pipelined instruction execution. Explain how this may happen in a DLX machine, and state ONE strategy that can be used to resolve the problem (6 marks) (b) Data hazards occur in instruction execution in a pipelined machine. () What is meant by...
A particular (fictional) CPU has the following internal units and timings: 1. IFD: Instruction fetch + decode : 160 ps 2. RR: Register read 80 ps 3. ALU: 240 ps 4. MA : memory access: 160 ps (assuming cache) 5. RW : register write : 80 ps There are 5 basic instruction types: 1. LOAD : IFD+RR+ALU+MA+RW 720 ps 2. STORE: IFD+RR+ALU+MA : 640 ps 3. ARITHMETIC: IFD+RR+ALU+RW : 560 4. BRANCH: IFD+RR+ALU : 480 ps 5. MEMOP: IFD+RR+MA+ALU+MA :...
Consider a hypothetical computer with an instruction set of only two n-but instructions. The first bit specifies the opcode, and the remaining bits specify one of the 2-1 n-bit words of main memory. The two instructions are as follows: SUBS X: Subtract the contents of location X from the accumulator, and store the result in location X and the accumulator JUMP X: Place address X in Program Counter A word in memory may contain either an instruction or a binary...
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