Vocabulary Exercises
Review Questions
Project
Compare Intel and AMD chips. Search terms such as “AMD Intel benchmark comparison.”
Answer)
1) RISC
RISC is otherwise known as the reduced instruction set computer which is defined to be a kind of computer instruction set which can help in displaying the computer's microprocessor for making smaller cycle per instruction (CPI) than that of a complex instruction set computer. This contains a smaller set of general and simple instruction which is much larger than the set of complex as well as specialized version.
2) MOVE
When there is a need for a movement of the data among the register, MOVE instruction is to be used which is considered as an instruction that is specified. This has been executed when the first operand would be equivalent to zero.
3) Wait states
This is considered as the delay of the computer processor which happens while accessing the external memory or for the other devices which are responding slow,
4) Word
This is defined to be the natural unit of the data that can be used for any of the design of the processor where the word size is called the number of bits processed by that of the computer's CPU completely.
5) Program status word
This is otherwise called as the PSW which is defined to be the collection of the data and has 8 byte long, this can be well maintained with regards to the OS which as a result keeps a track of the system's current behavior.
As per the Chegg policy, one question will be answered, whereas we have a tendency to do more for our students. We did five
Vocabulary Exercises A(n) __________ processor limits the number and type of complex instructions. A(n) __________ instruction...
Consider a hypothetical computer with an instruction set of only two n-but instructions. The first bit specifies the opcode, and the remaining bits specify one of the 2-1 n-bit words of main memory. The two instructions are as follows: SUBS X: Subtract the contents of location X from the accumulator, and store the result in location X and the accumulator JUMP X: Place address X in Program Counter A word in memory may contain either an instruction or a binary...
Assume the program counter (PC) is initially equal to n. Assume that the word length of the processor is 1. a) How many fetches are required to make PC equal to m if there are no branch instructions between n and m? b) What is the content of the instruction register (IR) when the PC’s value is n+k? Justify your answer. Why we are not using a hundred pipeline stages if anoperation can be divided up into a hundred steps,...
MARIE Assembly Code Problem For the following problem, please create new MARIE instructions by providing the full MARIE RTN (register transfer notation) for the described operation. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction) – refer to this as IR[11..0] and not X. Problem: LoadZero X – this is...
Vocabulary Exercises is the communication channel that connects all computer system components Cache types that are generally implemented on the same chip as the CPU include 3. thus controlling access to the bus by all other The CPU is always capable of being a(a) devices in the computer system. 4. An) is a reserved area of memory used to resolve differences in data transfer rate or data transfer unit size. 5. A(n) is an area of fast memory where data...
1) We would like to design a bus system for 32 registers of 16 bits each. How many multiplexers are needed for the design? Select one: 5 16 1 4 32 2) The basic computer can be interrupted while another interrupt is being serviced. Select one: True False 3) If the Opcode bits of an instruction is 111, then the basic computer instruction type is either memory-reference or input-output. Select one: True False 4) The content of AC in the...
Exercise 1. What is the size of the memory for the microprocessor if it has 24-bit address lines (bus)? Furthermore, give the starting address and the last address of the memory. 2. List the operation modes of the ARM Cortex-M3. 3. What is the function of register R13? Register R14? Register R15? 4. On an ARM Cortex-M3, in any given mode, how many registers does a programmer see at one time? 5. Which bits of the ARM Cortex-M3 status registers...
Questions1. The function L is defined as L(1) = 2,L(2) = 1,L(3) = 3,L(4) = 4 and for n ≥ 4,L(n + 1) = L(n) + L(n − 1) + L(n − 2)L(n − 3)i.e., the (n + 1)-th value is given by the sum of the n-th, n − 1-th and n − 2-th values divided by the n − 3-th value.(a) Write an assembly program for computing the k-th value L(k), where k is an integer bigger than...
The Fibonacci sequence F is defined as F(1) = F(2) = 1 and for n>= 2, F(n + 1) = F(n) + F(n − 1) i.e., the (n + 1)th value is given by the sum of the nth value and the (n − 1)th value. 1. Write an assembly program typical of RISC machines for computing the kth value F(k), where k is a natural number greater than 2 loaded from a memory location M, and storing the result...
26. The is a group of bits that tells the computer to perform a specific operation A). program counter B). Opcode C). register D). microoperation 27. A condition called occurs in unsigned binary representation of a number when the result of an arithmetic operation is outside the range of allowable precision for the given number of bits. A). underflow B). 2's complement C). overflow D) bitwise complement 28. An iteration of the fetch-decode-execute cycle includes which of the following events?...
Computer Architecture 14. Fill in the blanks below with the most appropriate term or concept discussed in this chapter: A. ---------------The time required for the first result in a series of computations to emerge from a pipeline. B. ---------------This is used to separate one stage of a pipeline from the next. C. ---------------Over time, this tells the mean number of operations completed by a pipeline per clock cycle. D. ---------------The clock cycles that are wasted by an instruction-pipelined processor due...