computer science question
draw all the AND, OR, and NOT gates to implement a 4×1 multiplexer. Label all inputs and outputs appropriately.
computer science question draw all the AND, OR, and NOT gates to implement a 4×1 multiplexer....
Problem 1. Sequential Circuit Design Using a decoder and AND gates, implement a 4-input multiplexer. . Using D-FFs, implement a 4-bit register. If using circuit verse, connect the Din signals to inputs blocks and connect Power to the enable lines. Do not forget the clock.
2. [15pt] Implement the following Boolean function using a multiplexer. f(xy.zw) m(0,2,5,8,10,14.15) Carefully label all the inputs and outputs of your multiplexer and justify your design.
Implement the function f (A,B,C,D) summation(m(0,2,5,8,12,13,14,15)) using: a. A 4-to-1 multiplexer, and external gates. Choose inputs A and B as the select lines. b. A 4-to-16 decoder and OR gate c. A PLA
Implement the function?(?, ?, ?) = ∑?(2,5,6,7)using one 4-to-1 multiplexer. You can use any other gates (AND,OR, Not , NoR).
Question 2: Combinational Logic (15 points) Implement the following Boolean function Z(A,B,C,D) = {(1,2,5,7,8,10,11,13,15) 2.1 (5 points) Write the truth table for Z. 2.2 (5 points) Implement Z using a single 16:1 multiplexer. Make sure that you mark all inputs and outputs clearly. 2.3 (5 points) Implement Z using an 8:1 multiplexer and all necessary gates. Make sure that you mark all inputs and outputs clearly.
Implement the function F (x,y,z)= (not x)(not z)+ xy using a. One 4-to-1 multiplexer and any additional inverters. Show your truth-table and justify your choice of select inputs. b. One 2-to-1 multiplexer and the minimal number of gates. Show the truth table used to derive your circuit.
Digital Circuits 1) Draw block diagrams to implement a 4 to 1 with 4 bits multiplexer. The data input lines are 4 bits wide. Please decide how many selects do you need. And write the final equation for inputs and output in both your report and block diagram. Do the simulation.
1. Implement the four-input odd-parity function with AND and OR gates using bubbled inputs and outputs. Note: Rather than draw inverters explicitly, a common practice is to add “bubbles” to the inputs or outputs of a gate to cause the logic value on that input line or output line to be inverted.
Design a 6 to 1 multiplexer (inputs A,B,C,D,E,F,S[2:0] and output Z) (a) Implement the 6 to 1 multiplexer using only CMOS NORs, NANDs and inverters. ( b) Implement the 6 to 1 multiplexer using only CMOS transmission gates and inverters. (c) Which approach is better and why?
Use Shannon’s expansion to implement the following function with a 4-1 multiplexer, using A and B as the control signals. You may also use any additional basic gates needed. ?(?,?,?,?) = ??? + ??? + ??? + ???