Question

If you can't follow the instructions provided for this pre-lab, please let someone else try it. R1 and R2 are for you to figure out base on the instructions below.

This is the q2n4401 code:

.model Q2N4401 NPN(Is=26.03f Xti=3 Eg=1.11 Vaf=90.7 Bf=378.9 Ise=183f Ne=1.433
+ Ikf=.3656 Nk=.5 Xtb=1.5 Var=100 Br=1.01 Isc=0 Nc=2 Ikr=0 Rc=.5
+ Cjc=11.01p Mjc=.3763 Vjc=.75 Fc=.5 Cje=24.07p Mje=.3641 Vje=.75
+ Tr=233.7n Tf=466.5p Itf=0 Xtf=0 Vtf=0)

Procedure In this pre-lab, you'll be designing 2 4-resistor bias configurations using a BJT and MOSFET. After completing your design by hand, you'll want to simulate the circuit in SPICE (using NETLIST code) to verify the DC operating points. Recall this can be accomplished using a.op command and looking at the output file. BJT Biasing Design a four resistor bias configuration as shown with the following constraints: Single 5 V power supply · Vo = 2.6V The BJT would remain in the forward active mode for Ve within the range of 1.6 to 3.6 V. Use the attached 2N4401 Spice model: g2n4401spicemodel.txt Use standard values resistors only (consult web for values) Bring the SPICE files with you to lab you will need them during the lab. For R1 and R2, design so that the total current through the first resistor is 10% of IC. . . R1

Answer 1

Edit the QbreakN model to PSPICE edit model with :
.model Q2N4401 NPN(Is=26.03f Xti=3 Eg=1.11 Vaf=90.7 Bf=378.9 Ise=183f Ne=1.433
+ Ikf=.3656 Nk=.5 Xtb=1.5 Var=100 Br=1.01 Isc=0 Nc=2 Ikr=0 Rc=.5
+ Cjc=11.01p Mjc=.3763 Vjc=.75 Fc=.5 Cje=24.07p Mje=.3641 Vje=.75
+ Tr=233.7n Tf=466.5p Itf=0 Xtf=0 Vtf=0)
then the transistor Q2N4401 will appear on the transistor. The solution is given below:

Solution: Rcquiremcnts: 0o0

OR Le 1、002 tC 1 โท 1-8

KML CW-イ

10K 11K 12K 13K 15K 16K 18K 20K 22K 24K 27K 30K 33K 36K 39K 43K 47K 51K 56K 62K 68K 75K 82K 91K 1.0K 1.1K 1.2K 1.3K 1.5K 1.6K 1.8K 2.0K 2.2K 2.4K FOR 32K : TAKE 16KX2QTY 1.1Kx1 QTY 2.4 x1 QTY. 18K x1 QTY 3.0K 3.3K 3.6K 3.9K 4.3K 4.7K 5.1K 5.6K 6.2K 6.8K 7.5K 8.2K 9.1K STANDARD RESISTOR VALUES WITH 5% TOLERANCE

OrCAD Capture Mirror Horizontally File Edit View Tools Place Macro PSpice Accessories Options Window Help cadence Mirror Vertically Mirror Both イ開イイ0 0 Edit Properties... Edit Part Export FPGA Show Footprint Edit PSpice Model Edit PSpice Stimulus Export Parameters to Optimizer Import Model Parameters.. Link Database Part View Database Part. Descend Hierarchy Synchronize Up Synchronize Down Synchronize Across Connect to Bus of cy, 0 SCHEMATIC!-SSSD ︾ Place Part cbjtbiasin... PAGE1* Part Edit pspice model of QbreakN Pait List: STIM16/SOURCE STIM4/SOURCE STIM8/SOURCE SUBPARAM/SPECIAL TANALOG TLOSSYPANALOG VAC/SOURCE R1 32k Ctri+D 다> ANALOG BREAKOUT Design Cache SOURCE SOURCSTM Add Part(s) To Group. Remoye Parts) From Group.. Ctr+Shift+R Assign Power Pins Ctri Shift A Packaging Paits per Pkg 1 Pat Ascend Hierarchy Selection Filter Fisheye view Zoom In Zoom Out Go To... Previous Page... Next Page. Type Homogeneous Noimal Conveit +Seach for Part Shift+F10 GND 0 circle in e Analog GND to the R2 18k F10 2 in your circuit ToolTip

Vcc RC 2.4k 5v R1 32 21 2N4401 R2 18k RE 1.1k CIRCUIT SIMULATION MODEL USING PSPICE

Simulation Settings SSSD General Analysis Configuration Files Options Data Collection Probe Window Analysis type Bias Point Options Output File Options Include detailed bias point information for nonlinear controlled sources and semiconductors(.0Pl Perform Sensitivity analysis (.SENS) Output variable(s Simulation settings to load Bias point General Settings Temperature Sweep) Save Bias Point □Load Bias Point □ Calculate small-signal DC gain LTF From Input source name To Output variable OK Cancel Apply Help

5.000V Vcc 102.5u R1 32k 983.5u RC 2.4k 1.086mA 0 2.640V 983.5u Q1 1.720 6.992uA Q2N4401 990.5uA GND 0 1.090V 95.53u 0V R2 18k 990.5u RE 1.1k Copy and paste the GND_0 circle in order to connect the Analog GND to the appropriate wires in your circuit. 0V 0 D.C Bias point analysis using PSPICE