Question

how to slove 4-25,26,27 ?? and please 2way slove state assignment gray code and counting Order

or tIne Circuit. snTor the (b) Find the state table for the circuit and make a state assignment (c) Find an implementation of the circuit using D flip-flops and logic gates 4-23. In many communication and networking systems, the signal transmitted on the communication line uses a non-return-to-zero (NRZ) format. USB uses a specific version referred to as non-return-to-zero inverted (NRZI). A circuit that converts any message sequence of Os and 1s to a sequence in the NRZ format is to be designed. The mapping for such a circuit is as follows: (a) If the message bit is a 0, then the NRZI format message contains an immediate change from 1 to 0 or from 0 to 1, depending on the current NRZI value. (b) If the message bit is a 1, then the NRZI format message remains fixed at 0 or 1, depending on the current NRZI value. This transformation is illustrated by the following example, which assumes that the initial value of the NRZI message is 1: Message: NRZI Message: 10100001000110 10001110011010 (a) Find the Mealy model state diagram for the circuit. (b) Find the state table for the circuit and make a state assignment (c) Find an implementation of the circuit using D flip-flops and logic gates W 4-24. +Repeat Problem 4-23, designing a sequential circuit that transforms an NRZI message into a normal message. The mapping for such a circuit is as follows: (a) If a change from 0 to 1 or from 1 to 0 occurs between adjacent bits in the NRZI message, then the message bit is a 0 (b) If no change occurs between adjacent bits in the NRZI message, then the message bit is a 1 A pair of signals Request (R) and Acknowledge (A) is used to coordinate transactions between a CPU and its I/O system. The interaction of these signals is often referred to as a "handshake." These signals are synchronous with the clock and, for a transaction, are to have their transitions always appear in the order shown in Figure 4-53. A handshake checker is to be designed that will verify the transition order. The checker has inputs, Rand A, asynchronous reset signal, RESET, and output, Error (E). If the transitions in a handshake are in order, E0. If the transitions are out of order, then E becomes 1 and remains at 1 until the asynchronous reset signal (RESET 1) is applied to the CPU 4-25 304 □ CHAPTER 4 /SEQUENTIAL CIRCUIis O FIGURE 4-53 Signals for Problem 4-25 (a) Find the state diagram for the handshake checker. (b) Find the state table for the handshake checker 4-26. A serial sequence detector is to be designed for some serial communication line that is able to detect a bit pattern of three, consecutive 1s connected with serial communication line and has output Z and input X When the input has three consecutive 1s then the output Z-0; in all other case, it will be zero. Once the output Z- 1, it will remain in state until some zero comes. Whenever0, the circuit reset. The circuit always remains in 0 states in all other bit sequence condition. Say after a bit sequence of O110, the circuit will go to initial state at the end of the last zerg, i.e, whenever it detects some zero. (a) Find the state diagram for the serial leading-1s detector. (b) Is this a Mealy or a Moore machine. *Asequential circuit has two flip-flops A and B, one input X, and one output Y. The state diagram is shown in Figure 4-54. Design the circuit with D lip-flops using a one-hot state assignment 00/101/0 11/0 10/0 FIGURE 4-54 State Diagram for Problem 4-27

Answer 1

4-25)

Consider the following data - Signals used to coordinate transactions between CPU and I/O system are Request (R) and Acknowledge (A). Inputs to the handshake checker are R, A, asynchronous reset signal RESET The output is Error (E) When the transitions for a handshake are in order E-o * When the transitions for a handshake are out of order E=1. The transition remains at 1, until an asynchronous reset signal RESET 1 is applied to the CPU Also, consider the figure 5-43, page 288 of the textbook. State diagram for the handshake checker: 100 x1/1 1x/1 0x/1 x0/1 11/0 01/0 0/o 001 010 11/O 00/o From the above state diagram the term x is dont care term. - Let, the sequence of states is 000, 001, 010. 011 and 100. The transitions between the states by R and A signals. - Here, if the transition takes place from one state to its next state, then the transition is in order - Otherwise, if the transition varies from one state to another state, then the transition is not in State table for the handshake checker: Present state Inputs Next state Output 0 0 0 0 0 0 0 0 0 0