Question

RISC machines than in superscalar processuIS. (c) Show the pipeline activity for the following code fragment with and without applying the delayed branch technique. Assume that there are three pipeline stages (fetch-decode, address calculation, data movement) for load and store instructions and two stages (fetch-decode, execute) for ALU instructions. Address Instruction Comment 100 LOAD RA,X X ->RA 101 LOAD RB,Y ADD RA,RB RA RB -> RA 102 103 104 JUMP 106 ADD RB,1 STORE Y, RB STORE X,RA RB-> Y 105 106 (10 marks) xecution of the code, memory locations X and Y con- tain 1 and 2, respectively. What are their respective values after the execution of the code with and without applying the delayed branch technique? (2 marks)

Answer 1

n the delaved banch te executed in the 4oflowin rManner eential sucesor dela banch taget y fakor ince ApD RA, RE has to be exected thi he placed inside he delan

2 F/o AC DM RA,RS STORE X, 2A banch te F/D IUMP to F/D F/P AC DM STORE 2A :0汁tout delayed beanch. beanch В 2 JUMP oc