MARIE Assembly Code Problem
For the following problem, please create new MARIE instructions by providing the full MARIE RTN (register transfer notation) for the described operation. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction) – refer to this as IR[11..0] and not X. Also, assume there is an additional register called the SP (stack pointer) which stores the address of the current top of a stack.
Problem:
Push X – push the datum at memory location X onto the top of the stack (note that SP is the current top, X will be pushed 1 address further in memory). Make sure you adjust the SP appropriately.
MARIE Assembly Code Problem For the following problem, please create new MARIE instructions by pr...
MARIE Assembly Code Problem For the following problem, please create new MARIE instructions by providing the full MARIE RTN (register transfer notation) for the described operation. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction) – refer to this as IR[11..0] and not X. Problem: ClearIndirect X – X is...
MARIE Assembly Code Problem For the following problem, please create new MARIE instructions by providing the full MARIE RTN (register transfer notation) for the described operation. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction) – refer to this as IR[11..0] and not X. Problem: LoadZero X – this is...
MARIE Assembly Code Problem For the following problem, please create new MARIE instructions by providing the full MARIE RTN (register transfer notation) for the described operation. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction) – refer to this as IR[11..0] and not X. Problem: ClearIndirect X – X is...
For questions 3-4, provide the full MARIE RTN (register transfer notation) for these new MARIE operations. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction) – refer to this as IR[11..0) and not X in your RTN. 3) AutoIncrLoad X - the autoincrement addressing mode is used to access a...
b. A microprocessor has an instruction set that consists of 117 instructions, which need fetch, decode, read operand, execute, write and interrupt stages. Assume that as an average, each stage requires three micro- operations to complete. Also, assume that the control memory is N bits wide (i.e., control field bits + address selection field bits + address-one bits + address-two bits N bits). The control field bits are 15 and there are 15 flags to be monitored. i. How many...
RISC machines than in superscalar processuIS. (c) Show the pipeline activity for the following code fragment with and without applying the delayed branch technique. Assume that there are three pipeline stages (fetch-decode, address calculation, data movement) for load and store instructions and two stages (fetch-decode, execute) for ALU instructions. Address Instruction Comment 100 LOAD RA,X X ->RA 101 LOAD RB,Y ADD RA,RB RA RB -> RA 102 103 104 JUMP 106 ADD RB,1 STORE Y, RB STORE X,RA RB-> Y...
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Spring CE4717 Language Processors Q1. Consider the following LEx program. return R1 return R2 return R3 return R4 return R5; return R6; IA-2a-z)[A-Za-z0-9]- -2 10-91+ 10-9a-EA-FI Ihi] [01] [01] 이삐 t Vtin) int main (void) int tcode; do f tcode -yylex()i printf ("token type td \"%s\"\n", tcode, yytext); ) while (tcode)i return 0; i. Explain the steps needed...
2. (a) Briefly describe the compiler-based register optimization technique (typically (4 marks) (b) Describe the delayed branch technique and explain why it is more common in (4 marks) tetch, indirect and moon used for RISC machines). (c) Show the pipeline activity for the following code fragment with and without applying the delayed branch technique. Assume that there are three pipeline stages (fetch-decode, address calculation, data movement) for load and store RISC machines than in superscalar processors. instructions and two stages...
Implement the following statements using MS430 assembly instructions. You may use more than one, but you should minimize the number of instructions required. You can use both native and emulated instructions. Use hex notation for all numbers 1. (a) Move the word located in register R14 to R15 (b) Increment the word in R6 by 2. (c) Perform a bitwise ANDing of the word located at address 0x0240 with the datum in R15, placing the results in R15. (d) Rotate...
Please answer the following Assembly x86 Questions with either TRUE or FALSE. 1. The PUSHAD instruction pushes all the 32-bit general-purpose registers on the stack. 2. The SS register points to the last value pushed on the stack. 3. The POP instruction copies a value from the stack to an operand, then it increments the stack pointer 4. When a macro is invoked, both CALL and RET instructions are needed. 5. When the instruction CALL runs, ESP always changes value....