Question

Write the HDL gate-level hierarchical description of a four-bit adder-subtractor for unsigned binary numbers. You can instantiate the four-bit full adder. Write a test bench to test your module.

Answer 1

module half_adder (input1, input2, sum, carry);
// I/0 declarations
input inputl, input2;
output sum, carry;
//instantiate gate primitives
xor xorl (sum,input1,input2);
and andl (carry,input1,input2);
endmodule

//Full Adder using half adder
module full_adder (input1,input2,carry_in,sum,carry_out);
// I/O declarations
input input1,input2,carry_in;
output sum,carry_out;
//internal signals declaration
wire xor_out,and1_out,and2_out;
//instatiation of half adder
half_adder half_adder1(input1,input2,xor_out,and1_out);
half_adder half_adder2 (carry_in,xor_out,sum,and2_out);
or (carry_out,and2_out,and1_out);
endmodule

module FourBit_AdderSub (input1,input2,carry_in,sum,carry_out);
// I/O declaration
input [3:0] inputl,input2;
output[3:0] sum;
output carry_out;
input carry in;
//internal signals declaration
wire c1,c2,c3,x0,x1,x2,x3;
//instantiate for full adders'
xor xora(x0,carry_in,input2[0]);
full_adder full_adder1 (input1[0],x0,carry_in,sum[0],c1);
xor xorb(x1,carry_in,input2[1]);
full_adder full_adder2(input1[1],x1,c1,sum[1],c2);
xor xorc(x2,carry_in,input2[2]);
full_adder full_adder3 (input1[2],x2,c2,sum[2],c3);
xor xord(x3,carry_in,input2[3]);
full_adder full_adder4 (input1[3],x3,c3,sum[3],carry_out);
endmodule

//Test Bench for the 4bit adder-subtractor

module FourBit_AdderSub_TB;
// Inputs
reg [3:0] input': reg [3:0] input2; reg carry_in;
// Outputs
wire [3:0] sum;
wire carryout;
// Instantiate the Unit Under Test (UUT)
FourBit_AdderSub uut
.inputl(input1),
.input2(input2),
.carry_in(carry_in),
.sum(sum),
.carry_out(carry_out)
);
reg [8:0] i;
initial begin
for (i = 0; i <= 511; i = i + 1) begin
input1[3:0] = 1[8:5]; input2 = i[4:1]; carry_in = 1[0]; #5;
end
end
endmodule