Question

Write a Verilog program to implement and test a subtractor. The program should have three modules. The first module, called cfulladder implements a one bit subtractor with two 1-bit outputs, S and Cout, and three one bit inputs A, B, Cin. You have to use always keyword to implement this combinational circuit. The second module, called sub4 implements a four bit subtractor by instantiating 4 cfulladder modules. It has the same inputs and outputs but now the S, A, and B are four bits wide, while the rest are still one bit The last module, called t_sub is a testbench. It instantiates one sub4 module and tests it for several possible inputs. Using the pre-lab as guide you define A and B as 4-bit registers and initialize them to zero. Then, using a repeat loop you increment A and B by 1 and 2 respectively and display the time, A, B, S and Cout, in this order as decimals. You repeat the loop 7 times. You have to have a 5 unit delay before every display instruction. All modules should be in one file

Answer 1

Design code:

design.sv 1//- 2timescale 1 ns / 1 ps 3 module cfulladder (A,B,Cin,s,Cout) 4 input A, B,cin; output reg S,Cout; always@(A or B or Cin) begin S-A A BA Cin Cout=(A & B) T (B & Cin) | (cin & A); end 11 endmodule//:cfulladder 12 //-- timescale 1 ns -Full_subtractor Design- 5 6 7 10 --4_bit_subtractor Design- /1 ps 13 14 module sub4 (A,B,Cin,S,Cout); input [3:01A, B; input Cin; output [3:0]s; output Cout; wire [3:1]C; 15 16 17 18 19 cfulladder f1(A[O] ,B[0],cin,S[0],C[1]); cfulladder f2 (A[1] ,B[1],c[1],S[1],c[2]D; cfulladder f3 (A[2],B[2],C[2],S[2],c[3]); cfulladder f4 (A [ 3] ,B[3] ,C[3],S[3],Cout); 24 endmodule//:sub4 20 21 22 23

Test bench code:

output:

testbench.sv 1//-- 2 timescale 1 ns/1 ps 3 module t_sub; reg [3:0]A, B; reg Cin wire [3:01S; wire Cout; --Test_bench-- 4 5 6 7 sub4 dut(A, B,Cin,s,Cout); initial begin $monitor("time=%d,A-%b, B%b,Cin=%b,S=%b,Cout=%b",$time,A,B,Cin,S,Cout); 9 10 A 4'b0000; B=4'b0000;cin-0; 11 repeat (7) begin #5 A-A+ 1 ; B-B+2 end end initial begin Sdumpfile "dump.vcd"); Sdumpvars (1) end 12 13 14 15 16 17 18 19 20 21 endmodule//:t_sub +

time time= 0,A 0000, B 0000,cin-0,S=0000,Cout-0 5,A 0001, B-0010,cin=0,S=0011, Cout-0 10,A 0010, B-0100,cin-0,S=0110,cout-0 15,A-0011, B-0110,Cin=0,S=1001, Cout-0 20, A-0100, B 1000,Cin=0,S=1100, Cout-0 25,A-0101, B=1010,cin=0,S=1111, Cout -0 30,A 0110, B=1100,cin-0,S-0010, Cout-1 35,A-0111, B-1110,cin=0,S-0101,Cout -1 time= time= time= time= time= time
waveform:
25,000 10.000 A[3:0] E[3:0] Cin s[3:01