Question

Problem 5: (2 x 5 marks) Perform technology mapping to NAND and NOR gates on the given circuit. You need to show 4 figures (as shown in Lecture#11, slide#7) a, b, c, d as part of your solution. A. Implementation with NAND gates B. Implementation with NOR gates A. B C I D G E F-

Please show all the steps? It is one question. If you can't do both, please do part B? Thanks!

Answer 1

5) Given Circuit:

AB(C+D) AND A. B C- D E F OR OR G = - AB(C+D)+AF(C+D)+E AND AF(C+D)

A) From the above Circuit G = AB(C+D)+AF(C+D)+E

G = (ABC+ABD)+(ACF+ADF)+E

G = ABC+ABD + ACF+ADF+E

[G']' = [(ABC+ABD + ACF+ADF+E)']' { We know that (P')'= P }

G = [(ABC)'(ABD)'(ACF)'(ADF)'(E)']'  { We know that (PQ)'= P' + Q' }

G = [(ABC)'(ABD)'(ACF)'(ADF)'(E)']'

Implementation of NAND Gates:

Given G = [(ABC)'(ABD)'(ACF)'(ADF)'(E)']'

(ABC)' NANDO BO CO G=[(ABC)'(ABD)'(ACF)'(ADF)'(E)']' NAND ko (ABD)' NANDO DO (ADF)': NAND FO (ACF)': NAND E! E O ...................

Explanation:
NAND gate is used to find the Product of Two literals P NAND Gate Q Output is (PQ)'

B) From the above NAND Implementation G = [(ABC)'(ABD)'(ACF)'(ADF)'(E)']'

G = [(A'+B'+C')(A'+B'+D')(A'+C'+F')(A'+D'+F')(E)']'   { We know that (PQ)'= P' + Q' }

G = [(A'+B'+C')'+(A'+B'+D')'+(A'+C'+F')'+(A'+D'+F')'+(E')']   { We know that (PQ)'= P' + Q' }

G = [(A'+B'+C')'+(A'+B'+D')'+(A'+C'+F')'+(A'+D'+F')'+E]  { We know that (P')'= P }

G = [{(A'+B'+C')'+(A'+B'+D')'+(A'+C'+F')'+(A'+D'+F')'+E}']'  { We know that (P')'= P }

G = [{(A'+B'+C')'+(A'+B'+D')'+(A'+C'+F')'+(A'+D'+F')'+E}']'

Implementation of NOR Gates:

AOH A B C (A'+B'+C) NOR G=[{(A'+B'+C')'+(A'+B'+D')+(A'+C'+F')+(A'+D'+F')'+E}'l' NORO (A'+B'+D')! NOR ANOR D D G'= {(A'+B'+C')'+(A'+B'+D')+(A'+C'+F')+(A'+D'+F')'+E}' (A+D'+F) NOR F (A'+C'+F)' NOR E E O

Explanation:

NOR gate is used to find the Sum of Two literals P NOR Gate Q Output is (P+Q)'