Question

Do Simulate a 4bit Ripple Carry adder in Simulink and generate the VHDL code to be implemented on DE2 board. Submit the VHDL code generated by the HDL coder and also screen shots from the DE2 board/ Quartus environment. 4 Bit Ripple Carry Adder A(3) B(3) A(2) B(2) A(1) B(1) A(0) B(0) А B A B Cout C64) А в A B C(3) C(2) C(1) C(O) Co Ci Со Ci Co Co Ci Cin S S S S Sum(3) Sum (2) Sum(1) Sum(0) Want to write a VHDL model for a 4 bit ripple carry adder. Logic equation for each full adder is: a xor b xor ci; <= (a and b) or (ci and (a or b)); sum <= CO

Answer 1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity rc_adder is
port( a : in std_logic_vector(3 downto 0);  
b :   in std_logic_vector(3 downto 0);  
s : out std_logic_vector(3 downto 0);   -- 4 bit sum
   c :  out std_logic   -- carry out.
);
end rc_adder;

architecture Behavioral of rc_adder is


signal c0,c1,c2,c3 : std_logic := '0';
begin  

--first full adder
s(0) <= a(0) xor b(0);  --sum calculation
c0 <= a(0) and b(0);   --carry calculation
--second full adder
s(1) <= a(1) xor b(1) xor c0;
c1 <= (a(1) and b(1)) or (a(1) and c0) or (b(1) and c0);
--third full adder
s(2) <= a(2) xor b(2) xor c1;
c2 <= (a(2) and b(2)) or (a(2) and c1) or (b(2) and c1);
--fourth(final) full adder
s(3) <= a(3) xor b(3) xor c2;
c3 <= (a(3) and b(3)) or (a(3) and c2) or (b(3) and c2);
--final carry assignment
c <= c3;
end Behavioral;

The test bench program used for testing the design is given below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--this is how entity for your test bench code has to be declared.
entity testbench is
end testbench;

architecture behavior of testbench is

signal a, b , s : std_logic_vector(3 downto 0) :=(others => '0');
signal c :  std_logic:='0';

begin
UUT : entity work.rc_adder port map(a ,b ,s ,c );
--definition of simulation process
tb : process
begin
a<="0010";  
b<="1001";  
wait for 2 ns;

a<="1010";  
b<="0011";
wait for 2 ns;

a<="1000";  
b<="0101";  
wait for 2 ns;

a<="1010";  
b<="0110";  

wait;
end process tb;

end;

#RCA_waveform:

At the time of modifying code,we  assign a,b,s,c as num1,num2,sum,carry respectively.

here in wave form, a =>num1; b=>num2; s=>sum; c=> carry.

Current Simulation Time: 1000 ns pns 1 ns 2 ns 3 ns 4 ns 5 ns 6 ns 7 ns 8 ns 9 ns 10 ns 10 8 10 10 6 8 9 3 5 num1[3:0] num2(3:0) El sum[3:0] 1! carry olco 6 11 13 13 8 1 o! c1 1 ol!c2 1 o ! c3 1