Question

Write a model of a counter which counts in the sequence mentioned below. The counter should use behavioral modeling andacase statement. Develop a testbench to test it.The testbench should display the counter output in the simulator console output. Simulate usingthe clock period of10 units for 200 ns. 000, 001, 011, 101, 111, 010, (repeat 000).The counter will have an enable signal (SW2), a reset signal (SW1), and a clock signal (SW15). The output of the counter will be on LED2-LED0.

Answer 1

the module of the counter using Verilog:

// Code your design here
module design_count(en,clk,reset,q);
input clk,reset,en;
output reg [2:0] q;
assign ram[0]=0;// storing count
assign ram[1]=1;
assign ram[2]=3;
assign ram[3]=5;
assign ram[4]=7;
assign ram[5]=2;
reg [2:0] count;
assign q=count;
reg [2:0] i;
reg [2:0] ram [6];// random memory
always@(posedge clk, negedge reset)
begin
if(en)// enable when 1
begin
if(!reset)// reset when 0
begin
count<=0;
i<=0;
end
else
begin
i<=i+1;
count<=ram[i];// counting
if(i==5)
i<=0;
end
end
else
count<=3'bxxx;
end
endmodule
  

testbench:

// Code your testbench here
// or browse Examples
module test();
reg clk,reset,en;
wire [2:0] q;
design_count d1(en,clk,reset,q);
initial
begin
clk=0;reset=1;en=1;
#5 reset=0;
#10 reset=1;en=1;
#200 $finish;
end
initial
forever
#5 clk=~clk;
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule

waveform: