Question

How propagation delay affects the operation of parallel adder, JK and T flip flops? Discuss.

Answer 1

Synchronous Counter

Synchronous Counters are supposed in light of the fact that the clock contribution of all the individual flip-flounders inside the counter are altogether timed together in the meantime by a similar clock flag

In the past Asynchronous parallel counter instructional exercise, we saw that the yield of one counter stage is associated straightforwardly to the clock contribution of the following counter stage, etc along the chain.

The consequence of this is the Asynchronous counter experiences what is known as "Spread Delay" in which the planning signal is postponed a division through each flip-flop.

Nonetheless, with the Synchronous Counter, the outside clock flag is associated with the clock contribution of EVERY individual flip-flop inside the counter so the majority of the flip-flops are timed together at the same time (in parallel) in the meantime giving a fixed time relationship. At the end of the day, changes in the yield happen in "synchronization" with the clock flag.

The consequence of this synchronization is that all the individual yield bits changing state at the very same time because of the basic clock motion with no progressively outstretching influence and consequently, no spread deferral.

Paired 4-bit Synchronous Up Counter

synchronous counter

It very well may be seen over, that the outside clock beats (heartbeats to be checked) are nourished specifically to every one of the J-K flip-slumps in the counter chain and that both the J and K inputs are for the most part integrated in switch mode, yet just in the principal flip-flop, flip-flop FFA (LSB) are they associated HIGH, rationale "1" enabling the flip-failure to flip on each clock beat. At that point the synchronous counter pursues a foreordained arrangement of states because of the basic clock flag, propelling one state for each heartbeat.

The J and K contributions of flip-flop FFB are associated specifically to the yield QA of flip-flop FFA, however the J and K contributions of flip-flops FFC and FFD are driven from discrete AND doors which are likewise provided with signs from the information and yield of the past stage. These extra AND doors create the required rationale for the JK contributions of the following stage.

In the event that we empower each JK flip-lemon to flip dependent on regardless of whether all former flip-flop yields (Q) are "HIGH" we can get indistinguishable tallying grouping from with the offbeat circuit however without the expansive influence, since each flip-flop in this circuit will be timed at the very same time.

At that point as there is no natural engendering delay in synchronous counters, since all the counter stages are activated in parallel in the meantime, the most extreme working recurrence of this sort of recurrence counter is a lot higher than that for a comparative offbeat counter circuit.

4-bit Synchronous Counter Waveform Timing Diagram

synchronous counter waveform

Since this 4-bit synchronous counter checks successively on each clock beat the subsequent yields tally upwards from 0 ( 0000 ) to 15 ( 1111 ). Hence, this sort of counter is otherwise called a 4-bit Synchronous Up Counter.

Nonetheless, we can without much of a stretch build a 4-bit Synchronous Down Counter by associating the AND doors to the Q yield of the flip-tumbles as appeared to deliver a waveform timing chart the switch of the abovementioned. Here the counter begins with the majority of its yields HIGH ( 1111 ) and it checks down on the use of each clock heartbeat to zero, ( 0000 ) before rehashing.

Paired 4-bit Synchronous Down Counter

synchronous down counter

As synchronous counters are shaped by associating flip-tumbles together and any number of flip-lemon can be associated or "fell" together to frame a "separate by-n" double counter, the modulo's or "MOD" number still applies as it accomplishes for offbeat counters so a Decade counter or BCD counter with tallies from 0 to 2n-1 can be worked alongside truncated successions. All we have to expand the MOD tally of an up or down synchronous counter is an extra flip-flop AND door crosswise over it.

Decade 4-bit Synchronous Counter

A 4-bit decade synchronous counter can likewise be manufactured utilizing synchronous double counters to create a tally grouping from 0 to 9. A standard twofold counter can be changed over to 10 years (decimal 10) counter with the guide of some extra rationale to actualize the ideal state grouping. In the wake of achieving the check of "1001", the counter reuses back to "0000". We presently have 10 years or Modulo-10 counter.

Decade 4-bit Synchronous Counter

decade synchronous counter

The extra AND doors distinguish when the tallying succession achieves "1001", (Binary 10) and causes flip-flop FF3 to flip on the following clock beat. Flip-flop FF0 flips on each clock beat. Subsequently, the tally is reset and begins once again at "0000" delivering a synchronous decade counter.

We could undoubtedly re-organize the extra AND entryways in the above counter circuit to deliver other consider numbers such a Mod-12 counter which checks 12 states from"0000″ to "1011" (0 to 11) and after that continues making them reasonable for tickers, and so on.

Setting off A Synchronous Counter

Synchronous Counters use edge-activated flip-slumps that change states on either the "positive-edge" (rising edge) or the "negative-edge" (falling edge) of the clock beat on the control input bringing about one single tally when the clock input changes state.

By and large, synchronous counters depend on the rising-edge which is the low to high progress of the clock flag and offbeat swell counters rely on the falling-edge which is the high to low change of the clock flag.

synchronous clock signals

It might appear to be irregular that swell counters utilize the falling-edge of the clock cycle to change state, yet this makes it simpler to interface counters together on the grounds that the most noteworthy piece (MSB) of one counter can drive the clock contribution of the following.

This works in light of the fact that the following piece must change state when the past piece changes from high to low – the time when a convey must jump out at the following piece. Synchronous counters as a rule have a complete and a convey in stick for connecting counters together without presenting any engendering deferrals.

Synchronous Counter Summary

At that point to abridge a portion of the central matters about Synchronous Counters:

Synchronous Counters can be produced using Toggle or D-type flip-flops.

Synchronous counters are less demanding to plan than offbeat counters.

They are called synchronous counters in light of the fact that the clock contribution of the flip-flops

are altogether timed together in the meantime with a similar clock flag.

Because of this basic clock beat all yield states switch or change at the same time.

With all clock inputs wired together there is no intrinsic engendering delay.

Synchronous counters are now and again called parallel counters as the check is nourished in parallel to every single flip-flop.

The innate memory circuit monitors the counters present state.

The tally succession is controlled utilizing rationale doors.

By and large quicker task might be accomplished contrasted with Asynchronous counters.