The Pentium 4 microprocessor have two 8 Kbyte, Level 1 caches – one for data and one for instructions.
However, a design team is considering another option – a single, 16 Kbyte cache that holds both instructions and data.
Additional specs for the 16 Kbyte cache include:
- Each block will hold 32 bytes of data (not including tag, valid bit, etc.)
- The cache would be 2-way set associative
- Physical addresses are 32 bits
- Data is addressed to the word and words are 32 bits
How many blocks would be in this cache?
How many bits of tag are stored with each block entry?
The Pentium 4 microprocessor have two 8 Kbyte, Level 1 caches – one for data and...
1. A cache holds 64 words where each word is 4 bytes. Assume a 32 bit address. There are four different caches a. A direct-mapped cache with block size = 16 words b. 2-way set-associative cache with block size = 8 words c. 4-way set-associative cache with block size=4 words d. A fully associative cache with block size = 16 words. Complete the table for each cache. Cache a Cache be Cache Cache de 16 Number of bits needed for...
Question 3: Consider a 32-bit physical address memory system with block size 16 bytes and a 32 blocks direct mapped cache. The cache is initially empty. The following decimal memory addresses are referenced 1020, 1006, 1022, 5106, 994, and 2019 Map the addresses to cache blocks and indicate whether hit or miss. Note: You must use the hexadecimal approach in solving this question. You must also show the computations of dividing the memory address into tag bits, cache index bits,...
Cache of 4096 blocks, a 4-word block size, and a 32-bit address, find the total number of sets and the total number of tag bits for caches that are direct mapped, four-way set associative, and fully associative.
Cache question computer architecture A cache holds 128 words where each word is 4 bytes. Assuming a 32-bit address, for each of the following organizations, complete the table. a.A direct-mapped cache with block size = 16words b.2-way set-associative cache with block size = 8words c.4-way set-associative cache with block size = 4words d.A fully associative cache with block size = 2words. Cache a Cache b Cache c Cache d total # bits for word & byte displacement # bits in...
) Consider an 8-way associative 64 Kilo Byte cache with 32 byte cache lines. Assume memory addresses are 32 bits long. a). Show how a 32-bit address is used to access the cache (show how many bits for Tag, Index and Byte offset). b). Calculate the total number of bits needed for this cache including tag bits, valid bits and data c). Translate the following addresses (in hex) to cache set number, byte number and tag (i) B2FE3053hex (ii) FFFFA04Ehex...
Given the following 16 bit numbers: A.) 0x8FFF B.) 0x1000 C.) Ox00FO D.) 0x0888 E.) 0xC000 F) 0x9000 . If the numbers are unsigned integers rank them from smallest to larest )rank them from smallest to largest 10. If the above number are signed integers (2's complement 11Acomputer has a 16 bit address field,is byte addressable, the word length is also 16 bits, 32 lines of direct mapped cache and each line of cache holds 8 bytes. A.) How many...
Question 28 7 pts Consider a byte-addressable computer with 24-bit addresses, a cache capable of storing a total of 64K bytes of data, and blocks of 32 bytes. If the computer uses direct mapping, the format of the memory address is as follows: bits for the tag field, bits for the cache block number, and bits for the block offset.
2. Suppose that a program does read operations on the following memory addresses (e.g., with “lb” or “lw” instructions): 248, 1312. Give the number of the memory block that each of these addresses belongs to, for each of the following memory block sizes. (a) block size of one word (4 bytes) (b) block size of eight words (32 bytes) 3. Give the position (or set) in the cache that would be checked on each of the read operations of question...
Suppose we have a 32-bit MIPS processor, which includes a 2-way set associative data cache with capacity 16384 bytes, 16 bytes block, and a least recently used (LRU) replacement policy. Assume that the cache is empty (all valid bits are 0) before the following code is executed. lw $t1, 0x1040($0) lw $t2, 0x2044($0) lw $t3, 0x3048($0) lw $t4, 0x1044($0) lw $t5, 0x504c($0) lw $t6, 0x3040($0) For each of the six assembly instructions above, state i) the set field value for...
question 2 and 3
2. Determine how many sets of cache blocks will be there for the following Cache memory size (in bytes) Direct Mapped Blocks Size (in bits) 32 64 218 2-way Set Associative Block Size (in bits) 32 64 A 2A6 [0.5 * 16 = 8] 4-way Set Associative Block Size (in bits) 32 64 SK 64K 256K 3. The physical memory address generated by a CPU is converted into cache memory addressing scheme using the following mapping...