Question

Verilog

Q1: In a Xilinx FPGA, what is a control set? What does it contain?

Q2: Xilinx says designs with asynchronous resets may use excess LUTs and registers.

Briefly explain why.

Answer 1

A control set is the grouping of control signals (set/reset, clock enable and clock) that drives
any given SRL, LUTRAM, or register. For any unique combination of control signals, a unique
control set is formed. The reason this is an important concept is registers within a 7 series
slice all share common control signals and thus only registers with a common control set
may be packed into the same slice. For example, if a register with a given control set has just
one register as a load, the other seven registers in the slice it occupies will be unusable.
Designs with several unique control sets may have many wasted resources as well as fewer
options for placement, resulting in higher power and lower performance. Designs with
fewer control sets have more options and flexibility in terms of placement, generally
resulting in improved results.
In UltraScaleTM devices, there is more flexibility in control set mapping within a CLB. Resets
that are undriven do not form part of the control set as the tie off is generated locally within
the slice. However, it is good practice to limit unique control sets to give maximum
flexibility in placement of a group of logic.