Question

code in Verilog please.

modify the code below to make a PCAdder to implement an adder that always adds one input by 4. And make testbench for testing of 2 cases. Thank you!

*CODE BELOW*

module PCAdder(PCResult, PCAddResult);

input [31:0] PCResult;

output reg [31:0] PCAddResult;

/* Please fill in the implementation here... */
  
endmodule

Answer 1

Verilog Module : PCAdder.v

`timescale 1ns / 1ps

module PCAdder(
input [31:0] PCResult,
output [31:0] PCAddResult
);
   assign PCAddResult=PCResult+4;

endmodule
Verilog Test bench :PCAdder_tb.v

`timescale 1ns / 1ps

module PCAdder_tb;

   // Inputs
   reg [31:0] PCResult;

   // Outputs
   wire [31:0] PCAddResult;

   // Instantiate the Unit Under Test (UUT)
   PCAdder uut (
       .PCResult(PCResult),
       .PCAddResult(PCAddResult)
   );

   initial begin
       // Initialize Inputs
       PCResult = 0;

       // Wait 100 ns for global reset to finish
      
       // Add stimulus here
      
       #100;
       PCResult=4; //Test case 1
       #100; //wait for 100 ns
       PCResult=12; //Test case 2
      
  
      

   end
  
endmodule