Question

Problem 4 Design the static complementary CMOS implementation of a 2-bit comparator circuit, where we have two inputs A and B (each is 2-bit wide) and the output 0 if A > B and output 1 if A B. Design the circuit for minimum delay (assuming a stage effort of 4) and driving a load of 10 fF. As part of the design you need to determine the width of all transistors You can use the following transistor parameters for the design-L = 0.25 micron, minimum transistor width = 0.3 micron. Rsq(NMOS) = 13 Kohm/sq. Rsq(PMOS) = 26 Kohm/sq, where the number of squares is equal to L/W, C9-1 fF/micron, C 1.5 fF micron. You can assume that you have both complemented and non-complemented inputs and that input signals have very small rise and fall times. Hint: Determine the Boolean expression of the comparator circuit and use the Boolean expression to design the circuit. Use logical effort technique to determine the transistor sizes. (Total: 25 points)

Answer 1

A. output (Y) AB tBCA+A) AtB circuit tofr 6