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Write a HDL code for 1 bit D-register with a rising edge clock, a synchronous active-low reset and an asynchronous active-hig

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Answer #1 
Program1:

 
Library IEEE;
USE IEEE.Std_logic_1164.all;

 
entity Rising Edge_DFlipFlop_Sync Active low Reset is 
   port(
      Q : out std_logic;    
      Clk :in std_logic;  
   sync_reset: in std_logic;  
      D :in  std_logic    
   );
end Rising Edge_DFlipFlop_Sync Active low Reset;
architecture Behavioral of Rising Edge_DFlipFlop_Sync Active low Reset is  
begin  
 process(Clk)
 begin 
    if(rising_edge(Clk)) then
   if(sync_reset='0') then 
    Q <= '0';
   else 
    Q <= D; 
end if;
    end if;       
 end process;  
end Behavioral; 
Program2:

 
Library IEEE;
USE IEEE.Std_logic_1164.all;

 
entity RisingEdge_DFlipFlop_AsyncResetHigh is 
   port(
      Q : out std_logic;    
      Clk :in std_logic;  
   sync_reset: in std_logic;  
      D :in  std_logic    
   );
end RisingEdge_DFlipFlop_AsyncResetHigh;
architecture Behavioral of RisingEdge_DFlipFlop_AsyncResetHigh is  
begin  
 process(Clk,sync_reset)
 begin 
     if(sync_reset='1') then 
   Q <= '0';
     elsif(rising_edge(Clk)) then
   Q <= D; 
  end if;      
 end process;  
end Behavioral;
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