Question

6. (20%) Write HDL code to synthesize the following circuits:

a. 8-bit register.

b. 9-bit Register with Asynchronous Reset

c. N-bit Register with Synchronous Reset where N is a parameter

d. N-bit register with Enable and Asynchronous reset where N is a parameter

e. 8-bit latch

Answer 1

//Part A)

module register_8bit (clk, in1, out1);
input clk;
input [7:0] in1;
output [7:0] out1;
reg [7:0] out1;

always @(posedge clk)
begin
out1 <= in1;
end

endmodule

//Part B)

module register_9bit (clk, rst, in1, out1);
input clk;
input rst;
input [8:0] in1;
output [8:0] out1;
reg [8:0] out1;

always @(posedge clk or posedge rst)
begin
if (rst == 1'b1)
out1 <= 9'd0;
else
out1 <= in1;
end

endmodule

//Part C)
module register_Nbit_sync (clk, rst, in1, out1);
parameter N = 8;
input clk;
input rst;
input [N-1:0] in1;
output [N-1:0] out1;
reg [N-1:0] out1;

always @(posedge clk)
begin
if (rst == 1'b1)
out1 <= 9'd0;
else
out1 <= in1;
end

endmodule

//Part D)
module register_Nbit_async (clk, rst, en, in1, out1);
parameter N = 8;
input clk;
input rst;
input en;
input [N-1:0] in1;
output [N-1:0] out1;
reg [N-1:0] out1;

always @(posedge clk or posedge rst)
begin
if (rst == 1'b1)
out1 <= 9'd0;
else if (en == 1'b1)
out1 <= in1;
end

endmodule

//Part E)

module latch_8bit (clk, in1, out1);
input clk;
input [7:0] in1;
output [7:0] out1;
reg [7:0] out1;

always @(posedge clk)
begin
out1 = in1;
end

endmodule