Question

Design a Verilog model that describes the following state diagram. (Test bench and simulation are not required) 1. 01 10 1- 10 10 01 01 10 or 01) 01 Design a Verilog model that describes a synchronous 3 bit counter. The counter has a counting mode control signal (M), when M-o, the counter counts up in the binary sequence, when M- 1, the counter advances through the Gray code sequence. (Test bench and simulation are required to verify the counter functionality) 1. Binary: 000, 001, 010, 011, 100, 101, 110, 111 Gray: 000, 001, 011, 010, 110, 111, 101, 100

Answer 1

Answer 1)

Verilog code

module state_diagram_moore (clk, rst, x, z);
input clk;
input rst;
input [1:0] x;
output [1:0] z;

parameter D = 2'b00,
A = 2'b01,
B = 2'b10,
C = 2'b11;

//Internal reg and wires decalarations
reg [2:0] cur_state, next_state;

// current state logic
always @(posedge clk)
begin
if(rst)
cur_state <= A;
else
cur_state <= next_state;
end

// Logic for next state and output
always @(*)
begin
case(cur_state)
A : begin
if (x == 2'b00)
next_state = C;
else if ((x == 2'b01) || (x == 2'b10))   
next_state = D;
end

B : begin
if (x == 2'b01)
next_state = A;
else if (x == 2'b10)   
next_state = B;
end

C : begin   
if (x == 1'b1)
next_state = D;
else if (x == 2'b00)
next_state = B;
else if (x == 2'b01)   
next_state = C;
end

D : begin
if (x == 2'b00)
next_state = B;
else if (x == 2'b01)   
next_state = D;
else if (x == 2'b10)   
next_state = C;
end

default : begin next_state = A; end
endcase
end

assign z = cur_state;

endmodule

Answer 2)

Verilog Code

module bin_gray_counter (clk, rst, M, count);
input clk;
input rst;
input M;
output [2:0] count;

parameter S0 = 3'b000,
S1 = 3'b001,
S2 = 3'b010,
S3 = 3'b011,
S4 = 3'b100,
S5 = 3'b101,
S6 = 3'b110,
S7 = 3'b111;

//Internal reg and wires decalarations
reg [2:0] cur_state, next_state;

// current state logic
always @(posedge clk)
begin
if(rst)
cur_state <= S0;
else
cur_state <= next_state;
end

// Logic for next state and output
always @(*)
begin
case(cur_state)
S0 : begin next_state = M ? S1 : S1 ; end
S1 : begin next_state = M ? S3 : S2 ; end
S2 : begin next_state = M ? S6 : S3 ; end
S3 : begin next_state = M ? S2 : S4 ; end
S4 : begin next_state = M ? S0 : S5 ; end
S5 : begin next_state = M ? S4 : S6 ; end
S6 : begin next_state = M ? S7 : S7 ; end
S7 : begin next_state = M ? S5 : S0 ; end
endcase
end

assign count = cur_state;

endmodule

Testbench for above code

module testbench;
reg clk, rst;
reg M;
wire [2:0] count;

bin_gray_counter DUT (.clk(clk), .rst(rst), .M(M), .count(count));

always
#5 clk = !clk;

initial
begin
clk = 1'b0;
rst = 1'b1;
M = 1'b0;
repeat(2)
@(negedge clk);
rst = 1'b0;
M = 1'b0;
repeat(16)
@(negedge clk);
M = 1'b1;
repeat(16)
@(negedge clk);
M = 1'b0;
repeat(7)
@(negedge clk);
$finish;
end
  
initial
begin
$recordfile("file1.trn");
$recordvars();
end

endmodule

@ Baseline▼.0 i Cursor-Baseline-55,000,000f Baseline - 100,000,000fs 200,000,000fs 0,000,000fs Name Cur 1 12 3 4 5 6 7 0 1 2 13 4 5 16 17 I0 1 13 I2 16 17 15 14 0 1 3 12 6 17 15 40 1 2 3 4 5 6 E,- > count 20]