3. Design a counter with the following repeated binary sequence: 0,1,2,4,6. Use D flip-flop.
4. Design a counter to count with T flip-flops that goes through the following binary repeated sequence: 0,1,3,7,6,4. Find out the counter response towards the unused state. Illustrate the response with a state diagram.
5. Design a mod-7 counter (repeat binary sequence: 0,1,2,3,4,5,6) use JK flip-flop.
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3)
Given sequence is
0 --- 1 --- 2 ---4 ---6,
Step1:State Transition table
we can make the state diagram as follows.
| Present State | Next State |
|---|---|
| 0 | 1 |
| 1 | 2 |
| 2 | 4 |
| 4 | 6 |
| 6 | 0 |
Step2:State Assignment,
The max number in the sequence is 6,so we need a minimum of 3 binary bits to represent each state.
| State | Assigned Binary Bits |
|---|---|
| 0 | 000 |
| 1 | 001 |
| 2 | 010 |
| 4 | 100 |
| 6 | 110 |
Step3:
writing the state Transition table by using State assignment,we get
| Present State | Next State | ||||
| Q2 | Q1 | Q0 | Q2+ | Q1+ | Q0+ |
| 0 | 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 |
Step4: Circuit excitation table:
TO build circuit excitation table, we need the excitation table of D flip flop,
| Present State | Next State | D flipflop Input(D) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Now, by considering the above excitation table, let us make our circuit excitation table, we get
Since we used three bits to represent each state, we need three flipflops.
| present state | Next state | D ff inputs | ||||||
| Q2 | Q1 | Q0 | Q2+ | Q1+ | Q0+ | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Step5:
Minimizing the above table by using any reduction techniques like kmap,
By using Kmap,
D2 with respect to Q2,Q2 and Q0,

D1 with respect to Q2,Q2 and Q0,

D0 with respect to Q2,Q2 and Q0,

4)
Given sequence is
0 --- 1 --- 3 ---7 ---6 ---4
Step1:State Transition table
we can make the state diagram as follows.
| Present State | Next State |
|---|---|
| 0 | 1 |
| 1 | 3 |
| 3 | 7 |
| 7 | 6 |
| 6 | 4 |
| 4 | 0 |
Step2:State Assignment,
The max number in the sequence is 6,so we need a minimum of 3 binary bits to represent each state.
| State | Assigned Binary Bits |
|---|---|
| 0 | 000 |
| 1 | 001 |
| 3 | 011 |
| 7 | 111 |
| 6 | 110 |
| 4 | 100 |
Step3:
writing the state Transition table by using State assignment,we get
| Present State | Next State | ||||
| Q2 | Q1 | Q0 | Q2+ | Q1+ | Q0+ |
| 0 | 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 |
| 1 | 1 | 1 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 |
Step4: Circuit excitation table:
TO build circuit excitation table, we need the excitation table of T flip flop,
| Present State | Next State | T flipflop Input(T) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Now, by considering the above excitation table, let us make our circuit excitation table, we get
Since we used three bits to represent each state, we need three flipflops.
| present state | Next state | T ff inputs | ||||||
| Q2 | Q1 | Q0 | Q2+ | Q1+ | Q0+ | T2 | T1 | T0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
Step5:
Minimizing the above table by using any reduction techniques like K-map,
By using K-map,
T2 with respect to Q2,Q2 and Q0,

T1 with respect to Q2,Q2 and Q0,

T0 with respect to Q2,Q2 and Q0,

5)Answer
Given sequence is
0 --- 1 --- 2 ---3 ---4 ---5---6
Step1:State Transition table
we can make the state diagram as follows.
| Present State | Next State |
|---|---|
| 0 | 1 |
| 1 | 2 |
| 2 | 3 |
| 3 | 4 |
| 4 | 5 |
| 5 | 6 |
| 6 | 0 |
Step2:State Assignment,
The max number in the sequence is 6,so we need a minimum of 3 binary bits to represent each state.
| State | Assigned Binary Bits |
|---|---|
| 0 | 000 |
| 1 | 001 |
| 2 | 010 |
| 3 | 011 |
| 4 | 100 |
| 5 | 101 |
| 6 | 110 |
Step3:
writing the state Transition table by using State assignment,we get
| Present state | Next State | ||||
| Q2 | Q1 | Q0 | Q2+ | Q1+ | Q0+ |
| 0 | 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 |
Step4:Circuit excitation table:
TO build circuit excitation table,we need the excitation table of JK flip flop,
| Present State | Next State | J | K |
|---|---|---|---|
| 0 | 0 | 0 | X |
| 0 | 1 | 1 | X |
| 1 | 0 | X | 1 |
| 1 | 1 | X | 0 |
Now,by considering the above excitation table,let us make our circuit excitation table,we get
Since,we used three bits to represent each state,we need three flipflops.
| Present state | next State | JK ff inputs | |||||||||
| Q2 | Q1 | Q0 | Q2+ | Q1+ | Q0+ | J2 | K2 | J1 | K1 | J0 | K0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | X | 0 | X | 1 | X |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | X | 1 | X | X | 1 |
| 0 | 1 | 0 | 0 | 1 | 1 | 0 | X | X | 0 | 1 | X |
| 0 | 1 | 1 | 1 | 0 | 0 | 1 | X | X | 1 | X | 1 |
| 1 | 0 | 0 | 1 | 0 | 1 | X | 0 | 0 | X | 1 | X |
| 1 | 0 | 1 | 1 | 1 | 0 | X | 0 | 1 | X | X | 1 |
| 1 | 1 | 0 | 0 | 0 | 0 | X | 1 | X | 1 | 0 | X |
Step5:
Minimizing the above table by using any reduction techniques like kmap,
By using Kmap,


D2 = Q2Q1Q0 +Q2Q1Q0
D2 = Q2Q1Q0 + Q2Q1Q0
Do = Q2Q1Qc
T2 = Q2Q1Q0 +Q22100
T1 = Q20100 +0201
T0 = Q22100 + Q2Q100
J2 = Q2Q100
K2 = Q1Q0
Jl = Q1Q0 K1 = Q200 + Q2Q0 JO=Q2+Q1 KO Q2 +01
3. Design a counter with the following repeated binary sequence: 0,1,2,4,6. Use D flip-flop.
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Design Problem: Use the JK Flip-Flop to design a circuit of a Synchronous Sequential Ring Counter that goes through the following sequence: 9, 8, 7, 13, 0, 11, 2, 5, 10, 14 and repeat ( forward direction ) Note: Your design should account for what happens if the systems starts at one of the unused states. In this scenario, the system should point to 0. The system has only one input, x. If x = 1, then the sequence goes...
3. Use the D-type flip-flops and logic gates to design a counter with the following repeated binary sequence: 0,2,1,3,4,7,5,6. Here, you need to use the best suited state encoding scheme to reduce the number of logic gates. Mention the encoding scheme you want to implement.
Design Problem: Use the JK Flip-Flop to design a circuit of a Synchronous Sequential Ring Counter that goes through the following sequence: 9, 8, 7, 13, 0, 11, 2, 5, 10, 14 and repeat ( forward direction ) Note: Your design should account for what happens if the systems starts at one of the unused states. In this scenario, the system should point to 0. The system has only one input, x. If x = 1, then the sequence goes...
Q1. Sequence Generator with flip-flop, counters 1. Use the minimum number of D flip-flops and logic gates to design a counter that produces the following repeated sequence: “0,1,3,5,6,7,0...” and gives an output of 1 when it reaches 7. (a) Show the state-table of the counter. (b) Show and simplify the K-Map for each flip-flop. (c) Implement the circuit derived in (b).
a counter to display the following sequence: 4,5,3,6, flip-flops in your design. Display the output using a 7-segment display. 1. Design 2, 7, 1, 0, and then repeat. Use JK
a counter to display the following sequence: 4,5,3,6, flip-flops in your design. Display the output using a 7-segment display. 1. Design 2, 7, 1, 0, and then repeat. Use JK
•Design a counter with repeated binary sequence 0,2,4,6,8 make the
table•From the table you made find the expression for the flip flop
input.•Draw the Kamaugh map for the flip flop Da,Db,Dc,Dd•Draw the logic diagram for the required counter.Please use the picture provided and write neat and clear as
possible. Thank you
verilog code needed for the counter using the JK flip
flop
please include the testbench, thanks!
Successfully completing a System Verilog +80Pts. Implementation showing the full sequence of ABC readouts Pre-Laboratory Exercise: You are to design a counter that will count through a sequence either forward or reverse. You will have two control inputs: Direction, and Reset'. Sequence #2: 000 100 110 111 101001 → 011 010 → 000... {Gray code} When Direction=0 follow the order listed above. When Direction...