Q1. Sequence Generator with flip-flop, counters 1. Use the minimum number of D flip-flops and logic...
Q1. Sequence Generator with flip-flop, counters
1. Use the minimum number of D flip-flops and logic gates to design a counter that produces the following repeated sequence: “0,1,3,5,6,7,0...” and gives an output of 1 when it reaches 7.
(a) Show the state-table of the counter.
(b) Show and simplify the K-Map for each flip-flop.
(c) Implement the circuit derived in (b).
Homework Answers
Add Answer to:
Q1. Sequence Generator with flip-flop, counters
1. Use the minimum number of D flip-flops and logic...
A. Design a circuit using D flip-flops that will generate the sequence 0, 0, 1, 0,...
A. Design a circuit using D flip-flops that will generate the
sequence 0, 0, 1, 0, 1, 1 and repeat. Do this by designing a
counter for any sequence of states such that the first flip-flop
takes on this sequence. There are many correct answers, but do not
duplicate states, because each state can have only one next
state.
B. A pulse-generating circuit generates eight repetitive pulses
as shown in the figure. Implement the pulse-generating circuit
using a binary counter...
3. Use the D-type flip-flops and logic gates to design a counter with the following repeated...
3. Use the D-type flip-flops and logic gates to design a counter with the following repeated binary sequence: 0,2,1,3,4,7,5,6. Here, you need to use the best suited state encoding scheme to reduce the number of logic gates. Mention the encoding scheme you want to implement.
3. Design a counter with the following repeated binary sequence: 0,1,2,4,6. Use D flip-flop.
3. Design a counter with the following repeated binary sequence: 0,1,2,4,6. Use D flip-flop. 4. Design a counter to count with T flip-flops that goes through the following binary repeated sequence: 0,1,3,7,6,4. Find out the counter response towards the unused state. Illustrate the response with a state diagram. 5. Design a mod-7 counter (repeat binary sequence: 0,1,2,3,4,5,6) use JK flip-flop.
Using all D flip-flops and combinational logic (AND/OR/NOT gates only) b) using all T flip-flop...
using all D flip-flops and combinational logic (AND/OR/NOT gates
only)
b) using all T flip-flops and a multiplexer of size 8:1
Problem 3: (10 pts) Design a synchronous machine (Transition Table, K-maps, Final Equations, Circuit Diagram) that counts through the following sequence in the order shown below. Note, there are no inputs or output variables, so your Q values must reflect the Hex value listed B 74 2 D9 3 0 and repeat a) using all D flip-flops and combinational...
7. JK flip-flops are often used to build counters. The JK flip-flop will toggle the original...
7. JK flip-flops are often used to build counters. The JK flip-flop will toggle the original output value when triggered by the clock signal if both the J.K inputs are connected with a constant "high"(logic 1). Suppose all the JK flip-flops in following Figure are positive edge triggered. The edges of the CLOCK are marked out in the figure. All the Qs have initial value 0. HIGH IFE CLOCK-HCL LK 000 0 0 0 Figure. Counter (a) Sketch the output...
a) (5 marks) Explain the difference between a latch, a gated latch and a flip flop....
a) (5 marks) Explain the difference between a latch, a gated latch and a flip flop. b) (5 marks) A gated SR latch has the following schematic diagram CLK a) Draw a timing diagram showing the Q and Q outputs for the following sequence of inputs: CLK R Assume that the initial state of the outputs is Q 0 and Q 1 c) (5 marks) Draw a schematic diagram for a rising edge-triggered master-slave D flip- flop built using two...
A pulse-generating circuit generates eight repetitive pulses as shown in the figure. Implement the pulse-generating circuit using the counter circuits listed and a minimum of gate logic. Use J-K flip...
A pulse-generating circuit generates eight repetitive pulses as shown in the figure. Implement the pulse-generating circuit using the counter circuits listed and a minimum of gate logic. Use J-K flip-flops for the counters that trigger on the falling edge of a clock that has a frequency eight times the frequency of one of the pulses. The pulses must be free of glitches; explain any restrictions on the propagation delays of gates and flip-flops so that the pulses will be glitch...
Objective: Design a 3-bit counters based on random number patterns using D flip- flop and other...
Objective: Design a 3-bit counters based on random number patterns using D flip- flop and other gates. The pattern of number is: 011 1. List state table. (3 points - writing for the report) 2. Using K-map, find relation among current state, input, and output. (3 points - writing for the report) 3. Draw circuits. (3 points - writing for the report)
(a) Design an asynchronous Binary Coded Decimal (BCD) count-up counter using JK flip-flops. Draw the counter circuit clearly showing the configuration of the JK flip-flops and the necessary logic gat...
(a) Design an asynchronous Binary Coded Decimal (BCD) count-up counter using JK flip-flops. Draw the counter circuit clearly showing the configuration of the JK flip-flops and the necessary logic gate(s). Sketch the input and output waveforms of this counter (7 Marks) (b) The binary up/down counter for a cargo lift controller in a 7-storey building has an up-down (UID) control input and a buzzer output (B). The buzzer will sound B 1) when the lift is at level 1 or...
Digital Logic Design Design a 0-9 counter using four D flip flops. The counter should run...
Digital Logic Design Design a 0-9 counter using four D flip flops. The counter should run on the SCLK output of the clock divider. It should have a four-bit binary output that increments from 0 to 9 one step on each clock cycle. When it reaches the value of 9, it should restart a 0 on the next clock cycle. Hint: consider using D flip flops with a reset input and using logic to reset the flip flops when the...
A. Design a circuit using D flip-flops that will generate the
sequence 0, 0, 1, 0, 1, 1 and repeat. Do this by designing a
counter for any sequence of states such that the first flip-flop
takes on this sequence. There are many correct answers, but do not
duplicate states, because each state can have only one next
state.
B. A pulse-generating circuit generates eight repetitive pulses
as shown in the figure. Implement the pulse-generating circuit
using a binary counter...
3. Use the D-type flip-flops and logic gates to design a counter with the following repeated binary sequence: 0,2,1,3,4,7,5,6. Here, you need to use the best suited state encoding scheme to reduce the number of logic gates. Mention the encoding scheme you want to implement.
using all D flip-flops and combinational logic (AND/OR/NOT gates
only)
b) using all T flip-flops and a multiplexer of size 8:1
Problem 3: (10 pts) Design a synchronous machine (Transition Table, K-maps, Final Equations, Circuit Diagram) that counts through the following sequence in the order shown below. Note, there are no inputs or output variables, so your Q values must reflect the Hex value listed B 74 2 D9 3 0 and repeat a) using all D flip-flops and combinational...
7. JK flip-flops are often used to build counters. The JK flip-flop will toggle the original output value when triggered by the clock signal if both the J.K inputs are connected with a constant "high"(logic 1). Suppose all the JK flip-flops in following Figure are positive edge triggered. The edges of the CLOCK are marked out in the figure. All the Qs have initial value 0. HIGH IFE CLOCK-HCL LK 000 0 0 0 Figure. Counter (a) Sketch the output...
a) (5 marks) Explain the difference between a latch, a gated latch and a flip flop. b) (5 marks) A gated SR latch has the following schematic diagram CLK a) Draw a timing diagram showing the Q and Q outputs for the following sequence of inputs: CLK R Assume that the initial state of the outputs is Q 0 and Q 1 c) (5 marks) Draw a schematic diagram for a rising edge-triggered master-slave D flip- flop built using two...
A pulse-generating circuit generates eight repetitive pulses as shown in the figure. Implement the pulse-generating circuit using the counter circuits listed and a minimum of gate logic. Use J-K flip-flops for the counters that trigger on the falling edge of a clock that has a frequency eight times the frequency of one of the pulses. The pulses must be free of glitches; explain any restrictions on the propagation delays of gates and flip-flops so that the pulses will be glitch...
Objective: Design a 3-bit counters based on random number patterns using D flip- flop and other gates. The pattern of number is: 011 1. List state table. (3 points - writing for the report) 2. Using K-map, find relation among current state, input, and output. (3 points - writing for the report) 3. Draw circuits. (3 points - writing for the report)
(a) Design an asynchronous Binary Coded Decimal (BCD) count-up counter using JK flip-flops. Draw the counter circuit clearly showing the configuration of the JK flip-flops and the necessary logic gate(s). Sketch the input and output waveforms of this counter (7 Marks) (b) The binary up/down counter for a cargo lift controller in a 7-storey building has an up-down (UID) control input and a buzzer output (B). The buzzer will sound B 1) when the lift is at level 1 or...
Most questions answered within 3 hours.
-
Where is the error in this code sequence?
String s1 = "Hello";
String s2 = "ello";...
asked 10 months ago -
Financial data for Joel de Paris, Inc., for last year
follow:
Joel de Paris, Inc.
Balance...
asked 10 months ago -
Consider this reaction:
Al2(SO4)3 (aq)+ BaCl3
(aq) Al2Cl6 (aq)- +
3BaSO4(s) . What is the...
asked 10 months ago -
Suppose that Savneet is considering increasing her
recent random sample from 20 car rentals to 40...
asked 10 months ago -
Trucks arrive at an unloading terminal at an average rate of 120
per hour.
Trucks arrive...
asked 10 months ago -
Why are methanol and ethanol completely soluble in water while
octanol is not very little soluble....
asked 10 months ago -
A facilities manager at a university reads in a research report
that the mean amount of...
asked 10 months ago -
When the CuSO4 is rehydrated by adding water to the anhydrous
compound, is this an endothermic...
asked 10 months ago -
A ray of sunlight is passing from diamond into crown glass; the
angle of incidence is...
asked 10 months ago -
A block of mass 0.249 kg is placed on top of a light, vertical
spring of...
asked 10 months ago -
how do the kidneys compensate in the presences of acidosis
a) trigger hyperventilate
b) reserve acid...
asked 10 months ago -
Question 501 pts
The rental rate of capital to the firm increases. Which of the
following...
asked 10 months ago