Question

3. Use the D-type flip-flops and logic gates to design a counter with the following repeated binary sequence: 0,2,1,3,4,7,5,6. Here, you need to use the best suited state encoding scheme to reduce the number of logic gates. Mention the encoding scheme you want to implement.

Answer 1

Giron, sequence: 0, 2, 1, 3, 4, 7, 5, 6 0-000 I-001 2 - 010 3-011 4-100 5-10 6-110 7-111 No of counts: + 8 so we need three flip flops. 1429,90 Excitation Equation of D-flip flop is D= ant state table with excitation inputs Present state | Next state I Inputs Oza , ao I a I at oot 102 O do o o o o 1 0 0 1 0 To i lo!! o 10 rooli ili Loi 1 1 0 1 0 1 10 To 0 0 Too 0 K-maps for D-inputs Doel 1 10 TOUT Jol 101 ID = 5 20 = G2 a, 50+ D2 = 0, 2, +9,90 Iz 5 got G20 Go + 0,99 Do = 92 (G, Qot G, Go) + 6, (5, Go + Q,00) Do = Q269,890) +62-C0,000) Scanned with Do = 9200, 20 CamScanner

AND gate CamScanner Scanned with XOR gete OR AND Jate gate DI , H D2 Tito CIK .