Question

Suppose you have a machine with separate I- and D- caches. The miss rate on the I-cache is 2.6% , and on the D-cache 3.8%. On an I-cache hit, the value can be read in the same cycle the data is requesfed. On a D-cache hit, one additional cycle is required to read the value. The miss penalty is 100 cycles for data cache, 150 for I-cache. 40% of the instructions on this RISC machine are LW or SW instructions, the only instructions that access data memory. A cycle is 1.5ns. What is the average memory access time?

Answer 1

EXPLANATION:

mem mod ind cache AOhen data is available miss thercoi'se a ns is hit hit katio het miss u 093-4 100 bit t miss A 2i970/11-09d of plab bsees3)0 yo)och Y Ld- Cache talo cPU baIS my bit ISTos5o Main memory की miss e cache १त5o)

SOLUTION:

40% of instructions access data memory, which refers to the D-cache.

Thus, rest 60% instructions lead to the I-cache.

Average memory access time refers to the time taken to read the data in every hit and miss in each cache.

cache (instruction cache) miss rate it dala read An same I50 miss rkes ality 40% ol total instructions D- cache Cdala cache) 3.8 % miss rate pendlly miss 100 to read dala additional egele reg 1-5 nsee time avg memard -1 2-6 % 91 (150 1-5) + 93.4% (.5) access x 66 3.8% (100 x 1-5) .62 (axi-5) 40 {(5.85+ 1-461)x 0. .142884)x04) + 4.3866 +3.4344 .821 nsec

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