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HW7.2.3) Which of the Verilog structural descriptions is equivalent to the following Verilog behavioral description? module...

HW7.2.3) Which of the Verilog structural descriptions is equivalent to the following Verilog behavioral description?

module hw7_2_3 (x1, x2, x3, f);

input x1, x2, x3;

output f;

always @ (x1, x2, x3)

if (x1 == 0)

f = x2 & ~x3;

else

f = ~x2 & x3;

endmodule

engineering   Electrical-Engineering   
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